I. INTRODUCTION

The Complementary Metal Oxide Semiconductor (CMOS) inverter is a fundamental digital circuit that combines one n-MOSFET and one p-MOSFET. Despite its simple operation that inverts the input signal and outputs it, the CMOS inverter is widely used across a broad range of process nodes from mature node and above to cutting-edge nodes due to its low power consumption and high-speed performance ^{[1- 5]}.

Especially among the various transistor structures adopted at nanometer technology nodes, Fully Depleted Silicon-On-Insulator (FDSOI) technology represents an attractive option for low-power integrated circuits. In FDSOI devices, a thin silicon film is electrically isolated from the substrate by a Buried Oxide (BOX) layer, enabling full depletion of the channel and tight electrostatic control.

Fig. 1. (a) CMOS inverter schematic, (b) FDSOI CMOS inverter structure.

However, FDSOI also has intrinsic drawbacks compared with bulk MOSFETs and Fin Field-Effect Transistors (FinFETs). The use of SOI wafers increases the substrate cost compared to bulk silicon wafers. Also, the low thermal conductivity of the buried oxide (BOX) suppresses efficient heat dissipation into the substrate, which leads to stronger self-heating than in fabricated on bulk silicon substrates during high current operation ^[6].

Despite these limitations, FDSOI devices provide significant advantages in terms of low power consumption and process simplicity compared with bulk MOSFETs and FinFETs. Compared with bulk MOSFETs, FDSOI devices exhibit lower leakage current and superior suppression of short-channel effects, enabling more energy-efficient designs ^{[7- 11]}. Unlike bulk FinFETs, FDSOI devices maintain a planar (2D) structure that closely resembles traditional CMOS processes, allowing easier integration and a simpler manufacturing flow ^{[12- 14]}. Additionally, its body biasing technology allows for flexible power and performance tuning, further reinforcing its advantage in process simplicity ^{[15- 17]}. Due to these strong advantages of FDSOI devices, continuous research is being conducted, and they are being utilized in various fields including CMOS inverter.

To individually optimize this CMOS inverter that consists of FDSOI devices for such various operating environments, numerous structural factors need to be considered. However, considering each of these factors using Technology Computer Aided Design (TCAD) simulation is inefficient due to a large number of repetitive simulations and restricted computing resources.

Recently, Artificial Intelligence (AI) has been considered a key approach to accelerating technological advancement. Accordingly, in the semiconductor industry, numerous research has been reported using deep learning algorithms to overcome the inefficiency of traditional optimization methods ^{[18- 27]}. However, there are no reported cases of optimizing the performance of CMOS inverters based on FDSOI devices structural parameters variation using a deep learning model trained on TCAD simulation data.

In this work, a novel approach to CMOS inverter optimization is proposed that applies Deep Learning (DL) algorithm which consists of neural network to overcome the inefficiency of the traditional methods. We aim to train a DL model to learn the performance variations of a CMOS inverter composed of 28 nm FDSOI device, as shown in Fig. 1(a), induced by changes in the structural parameters. This approach significantly reduces the computational resources required for optimization because the successfully trained DL model effectively predicts besides the given data, enabling performance predictions.

II. EXPERIMENTAL METHODS

To develop a DL model that can accurately predict the performance of a CMOS inverter, a flow chart described in Fig. 2 is used. And to obtain reliable data, the electrical and thermal characteristics of the simulation device are calibrated to the reference device according to the flow chart in Fig. 3(a). In the case of the electrical characteristics, the threshold voltage and subthreshold slope of the reference device are sufficiently reflected by fitting the transfer curve of the reference device, as shown in Fig. 3(b) ^[28]. And the FDSOI device has limited heat dissipation capability due to its buried oxide (BOX) layer, so accurate thermal calibration is required to reflect the vulnerability of self heating effect ^{[6, 29- 31]}. Therefore, to obtain more reliable simulation data, the thermal resistance data of the reference device are also fitted, as illustrated in Fig. 3(c) ^[32]. Therefore, Fig. 3(c) shows the effective thermal resistance of the reference device, extracted from the relationship between $\Delta T_{\text{max}}$ and power, which quantifies the temperature rise per unit power density. Because reducing self-heating increases carrier mobility, current, and thus power, it is difficult to judge from current and voltage curves alone whether the self-heating itself has decreased, so examining the temperature rise as a function of power provides a clearer measure of the intrinsic self-heating severity. A lower thermal resistance indicates weaker self-heating for the same power and thus enables more reliable electrothermal calibration of the simulation data ^[30].

Fig. 2. Flow chart of Deep Learning model.

Fig. 3. (a) Workflow for calibration, (b) Calibration of current properties to a reference [28], and (c) thermal resistance to a reference [32].

To describe the carrier transport mechanism, the drift-diffusion model is used. For improved accuracy, the Enormal (Lombardi), PhuMob, and high-field saturation mobility models to consider effects such as surface roughness scattering, impurity scattering, and velocity saturation are incorporated. The Shockley-Read-Hall (SRH) model is utilized to describe recombination processes, while the Oldslotboom model is applied to capture temperature- and doping-dependent bandgap narrowing effects ^{[33, 34]}. Additionally, the thermodynamic model is added to reflect for carrier dynamics influenced by the temperature gradient.

Fig. 4. Analysis of the FDSOI CMOS inverter at 10 GHz.

First, to generate the dataset for training the DL model, the Lightly Doped Drain (LDD) doping concentration (conc.) and Channel (CH) doping conc. are split within the range specified in Table 1. And then, AC simulations are conducted under a 10 GHz operating condition and three key performance metrics [Rising Time (RT), Falling Time (FT), and Power Loss ($P_{\text{Loss}}$)] are extracted. The RT and FT refer to the delay time required for the output voltage to transition between states. As illustrated in Fig. 4, these times are determined by calculating the delay time for the output voltage to change from A to B and C to D respectively. Points A and D correspond to 90 % of the maximum voltage ($V_{\text{max}}$), and points B and C are determined by subtracting 90 % of the voltage drop from $V_{\text{max}}$, as detailed in Eqs. (1) and (2).

And the $P_{\text{Loss}}$ is extracted by integrating the product of the supply voltage ($V_{DD}$) and the current provided by the PMOS over one cycle with respect to time. After that, Min-Max scaling is applied to the collected data to enhance the stability and efficiency of the DL model training ^[35]. And the data is divided into training, validation, and test sets in a 6:2:2 ratio. As illustrated in Fig. 5, the Deep Neural Network (DNN) architecture consists of an input, an output layer and three hidden layers which contain 128, 64 and 32 neurons, respectively. The input layer is 2-dimensional, representing the structural parameters, and the output layer is 3-dimensional, corresponding to the device performance metrics. To adopt non-linearity and effectively capture complex data patterns, the Rectified Linear Unit activation function is employed ^{[36, 37]}. And the DL model is set up to train for 150 epochs. For training, the Mean Squared Error (MSE), Adaptive Moment Estimation, and Mean Absolute Error (MAE) are adopted as the loss function and optimizer and metrics respectively ^{[38- 40]}. After training, multiple error metrics, including MSE, MAE, Root Mean Squared Error (RMSE), Root Mean Squared Logarithmic Error (RMSLE) and Coefficient of Determination($R^2$) are analyzed to select the optimal DL model for CMOS inverter data prediction.

Fig. 5. Deep Neural Network (DNN) architecture.

III. RESULTS AND DISCUSSION

1. Reliability of DL Model

In the proposed DL model, training is conducted using a regression-based approach. As training progresses, the weights of each neuron in the DNN are adjusted, allowing the predicted values to closely follow the training data. However, during this process, the model has the possibility of becoming excessively fitted to the training data, leading to overfitting, where significant errors occur when applied to unseen data ^{[41, 42]}. When overfitting occurs, train loss continues to decrease while test loss increases as the number of epochs increases. Therefore, it is crucial to monitor whether both train loss and test loss decrease together. To mitigate this issue, the proposed DL model employs a dropout technique, where 10 % of the neurons in each hidden layer are randomly deactivated, effectively preventing overfitting ^{[43- 45]}. As a result, as shown in Fig. 6, the train and test loss values decrease simultaneously as training progresses, leading to stable convergence at approximately epoch 100. To evaluate the model’s accuracy, MSE, MAE, RMSE, and RMSLE are confirmed, and their values are 0.0003596, 0.1881, 0.01281, and 0.01327, respectively. These values indicate that the model’s predictions have low error magnitudes across different evaluation criteria. The small MSE and RMSE suggest that large errors are minimal, while the MAE shows that the average absolute error remains low. Additionally, the low RMSLE implies that relative errors, particularly for smaller values, are well-controlled, further supporting the reliability of the model’s performance. These low values indicate that the prediction errors are small over the evaluated dataset. In addition, the training and validation loss curves decrease together and converge to similarly low values. This demonstrates that the proposed model achieves high accuracy without severe overfitting and can reasonably generalize to unseen data.

Fig. 6. MSE, MAE loss according to epoch.

Fig. 7. Coefficient of determination (R2) of (a) RT, (b) FT, and (c) PLoss.

Fig. 8. (a) RT, (b) FT, and (c) PLoss variations in actual and predicted values according to input data.

$R^2$ is also confirmed, as shown in Fig. 7(a)-(c), which presents the variance in the data. Unlike MSE and MAE etc., which only quantifies errors, it provides a relative measure of model performance by comparing it to a baseline (mean prediction) ^[46]. Eq. (3) represents the sum of squared residuals ($SS_{\text{Residual}}$), which is the sum of the squared differences between the actual values ($y_i$) and the predicted values ($\hat{y}_i$). A lower $SS_{\text{Residual}}$ indicates that the model accurately fits the actual data. Eq. (4) corresponds to the total sum of squares ($SS_{\text{Total}}$), which is the sum of the squared differences between the actual values ($y_i$) and the mean of the dataset ($\bar{y}$), representing the total variance in the data. As shown in Eq. (5), $R^2$ is defined as 1 minus the ratio of $SS_{\text{Residual}}$ to $SS_{\text{Total}}$, where this ratio quantifies the proportion of total variance that remains unexplained by the model. Consequently, a higher $R^2$ value indicates that the model effectively explains the variance in the data, with an $R^2$ value approaching 1 signifying a highly accurate representation of the complex patterns. As a result, the $R^2$ values of the output data (RT, FT and $P_{\text{Loss}}$) are 0.99013, 0.98619, and 0.99853, respectively, all of which are very close to 1, demonstrating the high reliability of the proposed DL model. Fig. 8(a)-(c) presents 3D distribution plots of actual and predict output data (RT, FT, $P_{\text{Loss}}$) as a function of input data (CH_Dop, LDD_Dop), intuitively confirming the high prediction accuracy of the DL model.

(3)

$SS_{\text{Residual}} = \sum_{i=1}^n (y_i - \hat{y}_i)^2,$

(4)

$SS_{\text{Total}} = \sum_{i=1}^n (y_i - \bar{y})^2,$

(5)

$R^2 = 1 - \frac{SS_{\text{Residual}}}{SS_{\text{Total}}}.$

Fig. 9. Trade off graph between PLoss and Delay Time which is sum of RT and FT.

IV. CONCLUSIONS

In this study, a reliable DL model is developed based on TCAD simulation data to improve the efficiency of CMOS inverter optimization, addressing the limitations of traditional optimization methods. The DL model’s reliability is validated through evaluation metrics such as MSE (0.0003596), MAE (0.1881), and $R^2$ (RT : 0.99013, FT : 0.98619, $P_{\text{Loss}}$ : 0.99853), all of which yielded reasonable values. Optimization is carried out from the perspective of $P_{\text{Loss}}$ and Delay Time, with the predicted data from the DL model closely matching the TCAD data with high accuracy. Additionally, the optimized point identified through the DL model shows a 69.4 % improvement in Delay Time and a 71.4 % improvement in $P_{\text{Loss}}$ compared to the reference structure. In future work, by leveraging this reliable DL model, we anticipate significantly reducing the time required for optimization by quickly predicting the desired $P_{\text{Loss}}$ and Delay Time values for CMOS inverters.