I. INTRODUCTION

Process, supply, and temperature (PVT) invariant voltage references are basic building blocks of many analog, digital, and mixed-signal systems including data converters. The need for low-power, low-area, and wide-temperature-range voltage references is evident in battery-operated and self-powered systems, portable devices, wearable biomedical applications, and wireless sensor networks ^{[1, 2]}.

Conventional bandgap references (BGRs), based on bipolar junction transistors (BJTs), offer excellent thermal stability but are limited by high power consumption and process incompatibility in advanced CMOS technologies. Traditionally, BJT circuits have been employed to generate PVT-independent bandgap references using a combination of complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltage/current generators ^[2]. These references utilize the negative temperature coefficient of the base-emitter voltage ($V_{BE}$) to generate CTAT voltage characteristics. However, the nonlinearity of $V_{BE}$ against temperature requires complex curvature compensation circuits to achieve a low temperature coefficient (TC) ^{[3, 4]}.

MOSFET circuits operating in the sub-threshold region are becoming popular due to their low-power and low-voltage operation ^{[5- 14]}. However, when resistors are included in the circuit, the chip occupies a large area ^[15]. To improve robustness against process variations, previous works ^{[16, 17]} proposed using identical PMOS transistors for $V_{th}$ generation and implementing a constant source-body bias. However, this approach introduces a trade-off, because an extra circuit branch is required to generate the bias voltage, resulting in a significant increase in power consumption.

In this article, an ultra-low-power, resistor-less, start-up-less, sub-1 V voltage reference based on a simple two-transistor CTAT voltage generator and a source-coupled differential-pair-based PTAT voltage generator is proposed. This configuration does not require start-up, complex current-reference, or trimming circuits, unlike the designs in ^{[18- 23]}. Specifically, the CTAT circuit utilizes two MOSFETs with different threshold voltages, which are typically available in most analog and digital CMOS processes. Many recent works do not achieve consistent performance over a wide temperature range, especially below $-20^\circ\text{C}$ or above $85^\circ\text{C}$. The proposed circuit utilizes CTAT and PTAT topologies with highly linear temperature dependence over a wide temperature range, thereby achieving a low TC.

II. CIRCUIT DESCRIPTION

The proposed sub-threshold CMOS voltage reference circuit topology is shown in Fig. 1. It consists of two core sub-blocks: a CTAT voltage generator and a PTAT generator. Both sub-circuits are implemented using MOSFETs operating in the sub-threshold (weak inversion) region, using long channel lengths to reduce leakage and enhance linearity. The circuit employs both standard- and high-threshold MOSFETs, which are available in most analog-friendly CMOS processes.

Fig. 1. Proposed voltage reference circuit.

1. CTAT Generator

The CTAT voltage generator uses two NMOS transistors in the same process, $M_1$ and $M_2$, with different threshold voltages, $V_{th1}$ and $V_{th2}$. These transistors are biased with equal gate voltages and operate in the sub-threshold region. $M_1$, $M_5$, and $M_6$ are chosen as standard-threshold NMOS devices, while $M_2$, $M_3$, $M_4$, and $M_b$ are high-threshold NMOS devices.

The CTAT circuit utilizes two MOSFETs operating in the sub-threshold region with different threshold voltages. For drain-to-source voltage greater than nearly 0.1 V, the sub-threshold current of a MOSFET is given by ^[8]

(1)

$I_{sub} = \mu C_{ox} K (\eta - 1) V_T^2 \exp\left(\frac{V_{gs} - V_{th}}{\eta V_T}\right),$

where $\mu$ is the mobility, $C_{ox}$ is the oxide capacitance per unit area, $K = (W/L)$ is the aspect ratio, $\eta$ is the sub-threshold slope factor, $V_T$ is the thermal voltage ($kT/q$), $V_{gs}$ is the gate-to-source voltage, and $V_{th}$ is the threshold voltage. Equating the currents in $M_1$ and $M_2$ leads to

(1)

$\mu_{n1} C_{ox1} K_1 (\eta_1 - 1) V_T^2 \exp\left(\frac{0 - V_{th1}}{\eta_1 V_T}\right) = \mu_{n2} C_{ox2} K_2 (\eta_2 - 1) V_T^2 \exp\left(\frac{V_{CTAT} - V_{th2}}{\eta_2 V_T}\right),$

(2)

$V_{CTAT} = (\eta_1 V_{th2} - \eta_2 V_{th1}) + \eta_1 \eta_2 V_T \ln\left[\frac{\mu_{n1} C_{ox1} K_1 (\eta_1 - 1)}{\mu_{n2} C_{ox2} K_2 (\eta_2 - 1)}\right].$

The absence of the power supply voltage ($V_{dd}$) term in Eq. (3) results in low line sensitivity (LS) and power supply ripple rejection (PSRR) characteristics. Typically, the threshold voltage of a MOS transistor exhibits a temperature dependence ^[24] as shown in Eq. (4), where $T$ is the temperature and $T_r$ is the reference temperature (usually $27^\circ\text{C}$). The value of $k_1$ is usually between $-0.3\text{ mV}/^\circ\text{C}$.

(3)

$V_{th}(T) = V_{th}(T_r) + k_1(T - T_r) = k_0 + k_1 T,$

where $k_0 = V_{th}(T_r) - k_1 T_r$.

However, in using two different MOSFETs $M_1$ and $M_2$ with different threshold voltages ($V_{th1}(T) = k_{10} + k_{11}T$, $V_{th2}(T) = l_{20} + k_{21}T$) having different temperature dependence factors ($k_{11}$ and $k_{21}$), the difference $\eta_1 V_{th2} - \eta_2 V_{th1}$ in Eq. (3) exhibits a CTAT nature

(4)

$\eta_1 V_{th2}(T) - \eta_2 V_{th1}(T) = \eta_1 k_{20} - \eta_2 k_{10} + (\eta_1 k_{21} - \eta_2 k_{11})T,$

Fig. 2. Analysis of CTAT voltage: (a) illustration of CTAT operation and (b) first derivative of VCTAT against temperature.

with the value of $\eta_1 k_{21} - \eta_2 k_{11}$ typically being negative. The values of $k_{11}$ and $k_{21}$ for standard $V_{th}$ and high $V_{th}$ MOSFETs in a typical 0.18-$\mu\text{m}$ process are $-0.43\text{ mV}/^\circ\text{C}$ and $-1.1\text{ mV}/^\circ\text{C}$, respectively (see Fig. 2(a)). The temperature dependency of $\mu_{n1}$ and $\mu_{n2}$ is ignored since the ratio $\mu_{n1}/\mu_{n2}$ is observed to be invariant with temperature. The aspect ratios of $M_1$ and $M_2$ are chosen so that the CTAT nature of the first term in Eq. (3) is predominantly stronger than the second term. In Fig. 2(a), the threshold voltage variation of MOSFETs $M_1$ and $M_2$ along with Eq. (5) are plotted against temperature, illustrating the CTAT generation and confirmed through simulation. Fig. 2(b) plots the first derivative of $V_{CTAT}$ against temperature demonstrating nearly constant slope over wide temperature range ($-50^\circ\text{C}$ to $150^\circ\text{C}$). For ultra-low power consumption, long channel lengths (supported by the process) shall typically be taken.

III. RESULTS AND DISCUSSION

The proposed resistor-less, sub-threshold CMOS voltage reference circuit was validated through extensive post-layout simulations using a 0.18-$\mu\text{m}$ CMOS process. Simulation results confirm the effectiveness of the CTAT and PTAT generators in achieving a highly stable reference voltage over a wide temperature range and under process variations. The results are presented and analyzed below.

Fig. 3(a) shows the reference voltage $V_{REF}$ as a function of temperature from $-50^\circ\text{C}$ to $150^\circ\text{C}$. The circuit achieves a minimal temperature coefficient (TC) of 5.5 ppm/$^\circ\text{C}$ across this range. Fig. 3(b) plots $V_{REF}$ against temperature at different $V_{dd}$ values of 0.8 V, 1.2 V, and 1.8 V, demonstrating strong resilience to supply variations. Corner simulations were performed to evaluate $V_{REF}$ stability. The maximum deviation observed in $V_{REF}$ was within 3% of the nominal value, ensuring robust performance across process variations. The line sensitivity (LS) of $V_{REF}$ was measured over a supply voltage range of 0.8 V to 3 V. As shown in Fig. 4(a), the LS was approximately 0.1%/V, indicating strong immunity to supply fluctuations. The PSRR of the proposed circuit was evaluated at 100 Hz and 1 MHz (Fig. 4(b)). The measured PSRR was $-53\text{ dB}$ at 100 Hz and $-18\text{ dB}$ at 1 MHz, indicating effective suppression of supply noise.

Fig. 3. Temperature dependence analysis: (a) $V_{REF}$ against temperature for the circuit shown in Fig. 1 at $V_{dd}$ = 1.2 V and (b) $V_{REF}$ against temperature at different $V_{dd}$ levels.

Fig. 4. Line sensitivity and PSRR analysis: (a) $V_{REF}$ against $V_{dd}$ at 27◦C and (b) PSRR against frequency.

Fig. 5(a) depicts $V_{REF}$ as a function of temperature for different process corners, highlighting the circuit’s consistent operation. The variation of temperature coefficient (TC) is observed to range from 5.5 ppm/$^\circ\text{C}$ to 28 ppm/$^\circ\text{C}$, illustrating low process sensitivity. Monte Carlo simulations (500 runs) were conducted to analyze the impact of process variations on $V_{REF}$ (Fig. 5(b)). The coefficient of variation ($\sigma/\mu$) is observed to be 2.76%, which is relatively low for threshold-voltage-based references ^[8]. The bias current showed a coefficient of variation of 3.5%, confirming tight control. For high-precision applications, the process variation of threshold voltage can be compensated by utilizing an analog adaptive-body-bias circuit proposed in ^[25]. The bias current and power dissipation of the proposed reference at $27^\circ\text{C}$ are 5.5 nA and 4.3 nW, respectively (at $V_{dd} = 0.8\text{ V}$). The circuit (layout shown in Fig. 6) occupies an area of $5315\ \mu\text{m}^2$. Simulations verified that all MOSFETs operate within safe voltage limits at a supply voltage of 3 V. The body-to-source junction voltages were analyzed to ensure that there is no forward biasing. The use of long-channel devices further mitigates the risk of breakdown.

Fig. 5(c) presents the Monte Carlo distribution of the Temperature Coefficient (TC) for 500 runs, evaluated at $V_{dd} = 1.2\text{ V}$. The results show a tightly clustered TC spread, indicating strong resilience to device mismatch and process variability. This further verifies the robustness of the temperature compensation strategy employed in the design. Fig. 5(d) illustrates the Monte Carlo analysis of Line Sensitivity (LS) at $27^\circ\text{C}$. The LS distribution remains narrow, demonstrating that the reference voltage exhibits minimal dependence on supply fluctuations even under statistical variations. This behavior is crucial for battery-powered and energy-harvesting applications, where supply noise and voltage drift are common. Fig. 5(e) shows the PSRR Monte Carlo results at $27^\circ\text{C}$ and $V_{dd} = 1.2\text{ V}$. The simulations confirm that PSRR remains consistently high across 500 runs, indicating that the reference effectively suppresses supply ripple despite device mismatches. The stable PSRR performance ensures reliable operation in mixed-signal environments where digital switching noise may couple into the supply.

Fig. 5. Monte Carlo analysis: (a) $V_{REF}$ against temperature with process variations. (b) distribution of rm$V_{REF}$ with process variations. (c) TC at $V_{dd}$ = 1.2 V for N = 500 runs. (d) LS at temp = 27◦C for N = 500 runs. (e) PSRR at temp = 27◦C and $V_{dd}$ = 1.2 V for N = 500 runs.

Fig. 6. Circuit layout.

Table 1 summarizes the performance of the proposed circuit compared with recent works. The design achieves a competitive TC of 5.5 ppm/$^\circ\text{C}$, low power consumption (4.5 nW), and a minimal area of $0.0053\text{ mm}^2$ (because of its simple structure). The proposed design demonstrates a strong balance between temperature stability, power efficiency, line sensitivity, and PSRR, closely matching several recent voltage reference circuits. The design is ideal for battery-operated and energy-harvested IoT nodes, biomedical implants, and low-voltage sensing applications.

IV. CONCLUSIONS

A highly linear CTAT topology based voltage reference circuit is proposed. The design presented is resistor-less (compatible with digital CMOS processes) and uses sub-threshold MOSFETS. It achieves sub-1V operation, low temperature coefficient, low area, low line sensitivity and low power dissipation. Further it does not require start-up, complex current reference or trimming circuits. Post layout analog simulations confirm the operation of the circuit and display improved results compared to similar recent works. Future work will explore the integration of curvature compensation techniques and short-channel devices to further optimize performance.