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Najafi M. H., Lilja D. J., Riedel M. D., Bazargan K., 2018, Low-cost sorting network circuits using unary processing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 8, pp. 1471-1480DOI
Li P., Lilja D. J., Qian W., Bazargan K., Riedel M. D., 2014, Computation on stochastic bit streams digital image processing case studies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 3, pp. 449-462DOI
Graefe G., Sep. 2006., Implementing sorting in database systems, ACM Computing Surveys, Vol. 38, No. 3, pp. 10DOI
Chang R. C., Wei M., Chen H., Lin K., Chen H., Gao Y., Lin S., 2014, Implementation of a high-throughput modified merge sort in mimo detection systems, IEEE Transactions on Circuits and Systems I, Vol. 61, No. 9, pp. 2730-2737DOI
Colavita A. A., Cicuttin A., Fratnik F., Capello G., 2003, Sortchip: a vlsi implementation of a hardware algorithm for continuous data sorting, IEEE Journal of Solid-State Circuits, Vol. 38, No. 6, pp. 1076-1079DOI
Tang Y., Bergmann N. W., 2015, A hardware scheduler based on task queues for fpga-based embedded real-time systems, IEEE Transactions on Computers, Vol. 64, No. 5, pp. 1254-1267DOI
KohÞtka L., StopjakovÃa˛ V., 2017, Rocket queue: New data sorting architecture for real-time systems, IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), pp. 207-212DOI
Yan J. T., 1999, An improved optimal algorithm for bubble-sorting-based non-Manhattan channel routing, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., Vol. 18, No. 2, pp. 163-171DOI
Campobello G., Russo M., Oct. 2006, A scalable VLSI speed/area tunable sorting network, J. Syst. Archit., Vol. 52, No. 10, pp. 589-602DOI
Tabrizi N., Bagherzadeh N., Oct. 2005, An ASIC design of a novel pipelined and parallel sorting accelerator for a multiprocessor-on-a-chip, in Proc. IEEE 6th Int. Conf. ASIC (ASICON), pp. 46-49DOI
Demirci T., Hatirnaz I., Leblebici Y., 2003, Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity, in International Symposium on Circuits and Signals, pp. 453-456DOI
Alaparthi S., Gulati K., Khatri S. P., 2009, Sorting binary numbers in hardware - A novel algorithm and its implementation, in International Symposium on Circuits and Systems, pp. 2225-2228DOI
Abdel-Hafeez S., Gordon-Ross A., 2017, An efficient o(n) comparisonfree sorting algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 6, pp. 1930-1942DOI
Ray S. S., Adak D., Ghoch S., Worst-Case O(N) comparison-free Hardware Sorting Engine, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, to be publishedDOI