Liu C.-C., Huang M-C., Feb. 2017, A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter, IEEE International Solid-State Circuits Conference, pp. 466-467

Li S., Qiao B., Gandara M., Pan D. Z., Sun N., Dec. 2018, A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure, IEEE Journal of Solid-State Circuits, Vol. 53, No. 12, pp. 3484-3496

Karmakar S., Gònen B., Sebastiano F., Van Veldhoven R., Makinwa K. A. A., Dec. 2018, A 280 μW dynamic-zoom ADC with 120 dB DR and 118 dB SNDR in 1 kHz BW, IEEE Journal of Solid-State Circuits, Vol. 53, No. 12, pp. 3497-3507

Shu Y.-S., Kuo L.-T., Lo T.-Y., Dec. 2016, An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 51, No. 12, pp. 2928-2940

Miyahara M., Matsuzawa A., Apr. 2017, An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier, IEEE Custom Integrated Circuits Conference, pp. 1-4

Akbari M., Honarparvar M., Savaria Y., Sawan M., Oct. 2020, OTA-free MASH 2-2 noise shaping SAR ADC: System and design considera-tions, 2020 IEEE International Symposium on Circuits and Systems, pp. 1-5

Zhang Q., Ning N., Li J., Yu Q., Wu K., Zhang Z., Jan. 2020, A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator, IEEE Transactions on Very Large Scale Integration Systems, Vol. 29, No. 1, pp. 227-231

Lin Y.-Z., Lin C.-Y., Tsou S.-C., Tsai C.-H., Lu C.-H., Feb. 2019, A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC with Passive Signal-Residue Summation in 14nm FinFET, IEEE International Solid-State Circuits Conference, pp. 330-332

Shiet L., Zhang Y., Wang Y., Kareppagoudr M., Sadollahi M., Temes G. C., Aug. 2018, A 13b-ENOB noise shaping SAR ADC with a two-capacitor DAC, International Midwest Symposium on Circuits and Systems, pp. 153-156

Jung H., Jeon N., Jang Y.-C., Oct. 2021, Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration, International SoC Design Conference, pp. 123-124

Jung H., Dec. 2020, Study on Second-order Noise Shaping SAR ADC, Master Degee, Kumoh National Institute od Technology

Park J., Nagaraj K., Ash M., Kumar A., Apr. 2017, A 12-/14-bit, 4/2MSPS, 0.085 mm2 SAR ADC in 65nm using novel residue boosting, IEEE Custom Integrated Circuits Conference, pp. 2152-3630

Guo W., Zhuang H., Sun N., Jun. 2017, A 13b-ENOB 173dB-FoM 2 nd-order NS SAR ADC with passive integrators, IEEE Symposium on VLSI Circuits, pp. c236-C237

Hsu C.-K., Tang X., Liu J., Xu R., Zhao W., Mukherjee A., Andeen T. R., Sun N., Mar. 2021, A 77.1-dB-SNDR 6.25-MHz-BW pipeline SAR ADC with enhanced interstage gain error shaping and quantization noise shaping, IEEE Journal of Solid-State Circuits, Vol. 56, No. 3, pp. 739-740

Zhang Q., Li J., Zhang Z., Wu K., Ning N., Yu Q., Ari. 2021, A 13b-ENOB third-order noise-shaping SAR ADC using a hybrid error-control structure, IEEE Custom Integrated Circuits Conference, pp. 1-2