I. INTRODUCTION

All signals existing in nature, such as sound intensity and temperature variations, manifest in the form of continuous and linear analog signals ^[1]. In contemporary times, electronic devices dedicated to processing diverse analog signals, including temperature fluctuations, biomedical signals, and images, have progressed significantly in terms of precision, power efficiency, and spatial utilization, among other performance metrics. This advancement not only contributes to the improvement of human life by enabling users to actively control their environment in expansive spaces through ubiquitous systems but also enhances experiences through smart systems that extend beyond simple voice information transmission ^[2,3]. The development of such technologies is no longer a matter of choice; it has evolved into an essential element, solidifying the interdependence between humans and electronic devices.

Digital devices interpret information through various signal processing technologies, including mathematical manipulation, conversion, exchange, transmission, and the storage of analog signals, tailored to specific objectives, ultimately delivering the processed information to users. The analog-to-digital converter (ADC) serves the purpose of converting multiple analog signals into digital form ^[4]. Analog-to-digital conversion stands as a crucial technology responsible for transforming analog signals acquired from sensors into a digital format. The performance of the ADC in this conversion process significantly impacts the accuracy and overall efficiency of the system. Consequently, enhancing the performance of ADCs is imperative in modern signal processing applications, prompting ongoing research into various ADC types ^[5,6].

Representative ADC methods employed in various systems include the successive approximation register (SAR) ADC, delta-sigma ADC, and pipeline ADC. SAR ADC, delta-sigma ADC, and pipeline ADC utilize distinct analog-to-digital conversion methods. SAR ADC operates by employing a binary search method to achieve accurate bit determination. It offers advantages such as high conversion speed and a simple circuit structure, but its applicability is limited to high resolution, and it exhibits a relatively small dynamic range ^[7,8]. Delta-sigma ADC achieves high resolution by shifting low-frequency noise out of the desired bandwidth through oversampling and noise shaping. It is characterized by high resolution, a wide dynamic range, and low power consumption but is associated with drawbacks such as slow conversion times and the necessity for high oversampling rates ^[9,10]. Pipeline ADC processes bits in parallel through multiple pipeline stages for simultaneous conversion. Its merits lie in fast conversion speeds and high performance, but it is marked by the challenges of complex circuit implementation and high-power consumption ^[11]. Fig. 2 illustrates the sampling rate, resolution, and corresponding features based on the ADC structure ^[12,13].

In this paper, we present the design of a delta-sigma ADC structure tailored for low-frequency signal measurements, encompassing DC measurements for temperature sensors, bridge sensors, and biometric signal sensors. Diverging from conventional delta-sigma ADCs, our approach introduces a second-order delta-sigma modulator with a differential difference amplifier (DDA) structure at the input stage. This design choice eliminates the necessity for an input buffer, consequently reducing both area requirements and power consumption.

Fig. 1. Various types of analog sensors.

Fig. 2. Characteristics based on the ADC structure.

II. ARCHITECTURE

The delta-sigma ADC can be broadly categorized into continuous-time (CT) type and discrete-time (DT) type based on how they process the analog input signal ^[14]. Fig. 3 illustrates the block diagrams of typical CT and DT delta-sigma modulators. The CT delta-sigma modulator continuously processes the incoming analog signal, with sampling taking place at the output of the quantizer before the loop filter. In contrast, the DT delta-sigma modulator discretely processes the analog signal through sampling at the input of the modulator.

The CT delta-sigma ADCs, owing to their continuous handling of the analog input signal, exhibit robustness to high-frequency signals and can effectively convert such signals. Additionally, their ability to employ high-order feedback filters aids in effectively eliminating noise and enhancing the accuracy of the desired signal, proving advantageous in high-performance ADC designs. Moreover, as the anti-aliasing filter (AAF) is integrated within the CT delta-sigma modulator, there's no need for a separate AAF design, and the input amplifier's design complexity is reduced due to the absence of sampling at the input.

However, due to the continuous signal processing and the use of high-order filters for performance enhancement, CT delta-sigma ADCs consume significant power and feature a relatively complex circuitry, leading to larger footprint consumption. Furthermore, in the low-frequency band, the effectiveness of high-order filters diminishes, impacting low-frequency performance. Additionally, difficulties in signal timing synchronization during the feedback signal transmission via the digital-to-analog converter (DAC) for sampling and vulnerability to clock jitter noise are notable ^[15].

On the other hand, the DT delta-sigma modulator samples the input signal at regular intervals and converts it into a digital signal through holding functions. Therefore, as long as the signal is determined within the sampling time, it shows resilience to clock jitter and maintains high stability. While its performance at high frequencies might relatively lag compared to CT delta-sigma modulators, its simpler circuitry facilitates easier design and production, resulting in reduced footprint and lower power characteristics ^[16]. In this paper, we employ the DT delta-sigma modulator structure for low-frequency input signals, aiming for low power consumption and smaller footprint characteristics.

The DT delta-sigma ADC samples the input signal using capacitors. However, the DC level of the input signal can be altered by these capacitors, potentially affecting low-frequency performance. Moreover, a problem arises with reduced input impedance leading to increased signal nonlinearity. To address these issues, conventional DT delta-sigma ADCs typically incorporate an input buffer before the modulator stage. While adding an input buffer provides various advantages to the delta-sigma ADC system ^[17-19], there may be several disadvantages. Firstly, there's additional area and power consumption. Integrating an input buffer increases the overall chip area of the system, especially when designing a high-performance input buffer with a complex structure, requiring additional transistors and circuits, thus consuming extra area and power to drive it. Secondly, there's a response time delay. Adding an input buffer can increase the overall response time delay of the system. This delay occurs as the input signal passes through the buffer, posing particularly critical issues in high-speed applications ^[20,21].

This paper proposes a second-order delta-sigma modulator based on a differential difference amplifier (DDA) without an input buffer. Fig. 4 shows a block diagram of the proposed circuit. The suggested second-order delta-sigma modulator is configured with a DDA structure at the input stage, providing very high input impedance characteristics. Additionally, since the input is separated from the feedback stage containing capacitors, it enhances resistance to high-frequency signals. Therefore, the proposed second-order delta-sigma modulator does not require an input buffer and can reduce additional area and power consumption associated with the use of an input buffer ^[22].

Fig. 3. Block diagrams of the delta-sigma modulator: (a) CT type; (b) DT type.

Fig. 4. Block diagram of the proposed second-order delta-sigma ADC based on differential difference amplifier.

III. CIRCUIT DESCRIPTION

1. Overall Circuit Design

Fig. 5 illustrates the overall circuit of the proposed second-order delta-sigma modulator based on DDA. The proposed circuit employs two integrators to form the loop filter and consists of a latched comparator comprising a pre-amplifier and latch for quantization, along with sub-blocks. Switches, functioning as 1-bit DACs controlled by the digital output of the modulator, transmit feedback signals to the two integrators. The clock signal applied to the switches is designed as a non-overlapping clock, ensuring stability and signal accuracy between the two clock signals.

The first integrator is configured in a discrete-time form as a differential difference amplifier structure, separating the paths of the input and feedback signals to provide a high-impedance input stage ^[23]. The second integrator is designed in a discrete-time fully differential (FD) amplifier structure, employing a CMOS rail-to-rail input structure and a gain-boosting amplifier circuit to accurately handle a variety of input signal ranges and increase the amplification of small input signals ^[24].

The proposed second-order delta-sigma modulator was modeled using MATLAB/Simulink, and the capacitor values, as per the modeling, are provided in Table 1.

The clock timing diagram for the proposed second-order delta-sigma modulator is shown in Fig. 6(a). The two integrators in the proposed modulator operate in opposite phases. The first-stage integrator, in a discrete-time differential difference amplifier structure, continuously accepts input signals over time at the input stage. For the feedback stage, during the Ф$_{1}$ phase, it resets the voltages at both ends of capacitor C$_{1}$ to VCM. In the Ф$_{2}$ phase, it receives the feedback signal from the output of the delta-sigma modulator and passes its output to the next stage.

The second-stage integrator, in a discrete-time fully-differential difference amplifier (FDDA) structure, during the Ф$_{2}$ phase, stores the output of the first-stage integrator and the feedback signal from the output of the delta-sigma modulator in capacitors C$_{3}$ and C$_{4}$, respectively. During the Ф$_{1}$ phase, it integrates the stored signals and forwards the result as the input to the quantizer.

Fig. 6(b) enlarges the clock timing diagram for the delta-sigma modulator. The input clock used for the proposed delta-sigma modulator switches is generated through a timing generator. The timing generator employs a relaxation oscillator to generate the main clock, which is then divided using a D flip-flop to produce a clock of the desired frequency. All clocks are designed as non-overlapping. Ф$_{1}$ and Ф$_{2}$ are configured as non-overlapping clocks to prevent unpredictable circuit behavior in regions where the rising edge and falling edge of the clock overlap. Ф$_{1d}$ and Ф$_{2d}$ operate in the same phase as Ф$_{1}$ and Ф$_{2}$, respectively, but their rising edges start slightly earlier than those of Ф$_{1}$ and Ф$_{2}$. This design enhances accuracy regarding voltage changes occurring in capacitors due to the switches and helps prevent unstable operation. Consequently, Ф$_{1}$ and Ф$_{2}$, and Ф$_{1d}$ and Ф$_{2d}$ are all non-overlapping clocks with none of the four signals sharing rising edge and falling edge times.

Fig. 5. The overall circuit of the proposed second-order delta-sigma modulator.

Fig. 6. (a) Timing diagram; (b) Enlarged timing diagram.

Table 1. The capacitor sizes of the proposed modulator

Parameters	Values
Capacitor 1 (C1)	1.2 pF
Capacitor 2 (C2)	10 pF
Capacitor 3 (C3)	1.4 pF
Capacitor 4 (C4)	0.6 pF
Capacitor 5 (C5)	3 pF

2. First-stage Integrator

Fig. 7 depicts the circuit of the first-stage integrator in the proposed second-order delta-sigma modulator. Signals from sources such as bio, temperature, and humidity exhibit small amplitudes ranging from hundreds of ${\mu}$V to a few mV, coupled with low-frequency characteristics. To accurately capture these small signals, a high voltage gain is essential. The first-stage integrator of the proposed delta-sigma modulator features a rail-to-rail input stage to reliably accommodate inputs with diverse characteristics. Additionally, a folded-cascode structure is applied in the middle stage to leverage high DC gain and unity gain bandwidth advantages. A gain-boosting amplifier circuit is also integrated to design the integrator for sufficient amplification of weak input signals. The output stage employs a class-AB structure for linearity and low power consumption characteristics.

To maintain a constant common-mode voltage, a common-mode feedback (CMFB) circuit is incorporated into the output stage of the first-stage integrator in the proposed delta-sigma modulator. If the common-mode voltage of V$_{OUTP}$ and V$_{OUTN}$ rises, the voltages of the two resistors, R, connected to the CMFB circuit also increase. Consequently, the gate voltage of the connected NMOS increases, leading to a decrease in the drain voltage CMFB\_OUT of the NMOS. As a result, the gate voltage of the PMOS positioned at the top of the middle stage amplifier decreases, causing a decrease in the common-mode voltage of the output V$_{OUTP}$ and V$_{OUTN}$. This CMFB circuit ensures that the output voltage maintains a constant common-mode voltage, and even if the common-mode voltage of the input changes, the output remains nearly unchanged.

Fig. 8 shows the results of the stability simulation of the first-stage integrator. Fig. 8(a) and (b) show the gain and phase characteristics of the first-stage integrator, respectively. The open loop gain is about 162 dB, and the unit gain bandwidth is about 2.1 MHz.

Fig. 7. Schematic of the first-stage integrator.

Fig. 8. Stability simulation results of the first-stage integrator: (a) open loop gain; (b) phase.

3. Second-stage Integrator

Fig. 9 illustrates the circuit of the second-stage integrator in the proposed second-order delta-sigma modulator. Structurally similar to the first-stage integrator, it employs a folded-cascode configuration to capitalize on high DC gain and unity gain bandwidth advantages. The circuit's gain is further enhanced through a gain-boosting amplifier, and a class-AB output stage ensures linearity and low-power characteristics. A CMOS input stage, composed of PMOS and NMOS, is designed to expand the input range sufficiently to handle the output range of the first-stage integrator. Operating as an FDDA, the second-stage integrator incorporates a CMFB circuit to maintain a constant common-mode voltage at the output, similar to the CMFB circuit in the first-stage integrator.

Fig. 10 shows the results of the stability simulation of the first-stage integrator. Fig. 10(a) and (b) show the gain and phase characteristics of the first-stage integrator, respectively. The open loop gain is about 148 dB, and the unit gain bandwidth is about 0.6 MHz.

Fig. 9. Schematic of the second-stage integrator.

Fig. 10. Stability simulation results of the second-stage integrator: (a) open loop gain; (b) phase.

4. Comparator

Fig. 11 illustrates the comparator circuit, functioning as the quantizer in the proposed second-order delta-sigma modulator. The comparator comprises a preamp stage and a latch stage. In the preamp stage, the common-source (CS) amplifier structure of the input stage amplifies the voltage difference of the signals entering V$_{INP}$ and V$_{INN}$, facilitating effective comparison. The positive feedback loop at the bottom quickly biases the V$_{OP}$ and V$_{ON}$ voltages generated by the CS amplifier, aiding the preamp stage in swiftly discerning subtle signal differences in the latch stage.

In the latch stage, when the control signal CLK is set to 1, both the sourcing current source, M$_{SRC}$, and the sinking current source, M$_{SINK}$, are turned off, rendering the circuit inactive. Furthermore, the connected NMOS to V$_{OUTP}$ and V$_{OUTN}$ is turned on, fixing the output voltage at 0 V. As CLK transitions to 0, the connected NMOS to V$_{OUTP}$ and V$_{OUTN}$ is turned off, allowing the output node to become variable, and M$_{SRC}$ and M$_{SINK}$ are turned on, enabling the normal operation of the circuit. If V$_{OP}$ has a slightly higher voltage than V$_{ON}$, relatively more current flows through the V$_{ON}$ line, causing the voltage at V$_{OUTP}$ to be slightly higher than that at V$_{OUTN}$. Subsequently, due to latch operation, the V$_{OUTP}$ node rapidly transitions to VDD, and the V$_{OUTN}$ node transitions to ground, executing the comparator operation ^[25].

Fig. 11. Schematic of the comparator.

IV. MEASUREMENT RESULTS

Fig. 12 displays a chip photograph of the fabricated second-order delta-sigma modulator circuit. The proposed circuit in this paper was manufactured using the TSMC 0.18-${\mu}$m 1P6M RFCMOS process. The overall chip size is 5 mm ${\times}$ 3.25 mm, and the active area of the implemented delta-sigma modulator is 1.049 mm ${\times}$ 0.534 mm (approximately 0.56 mm$^{2}$), with the combined active area including sub-blocks being around 0.8 mm$^{2}$. The chip integrates the delta-sigma modulator, I/V reference, timing generator, serial peripheral interface (SPI), and other components into a single chip.

Fig. 13 depicts the schematic diagram of the designed and fabricated second-order delta-sigma modulator circuit for measurement. The manufactured chip was mounted onto a printed circuit board (PCB) through the chip-on-board (CoB) process for measurements. To supply power, a DC power supply delivered a 3.3 V power voltage to the PCB, and a low-drop output voltage regulator within the PCB provided a 1.8 V power voltage. The Arduino Due and a laptop were employed to communicate with the chip's built-in SPI for controlling register inputs of the circuit. The input signal applied to the fabricated chip was generated and fed through a spectrum analyzer, while the output signal was measured in both time-domain and frequency-domain using an oscilloscope and a spectrum analyzer.

Fig. 14 illustrates the transient simulation results of the input and output signals applied to the fabricated second-order delta-sigma modulator. In Fig. 14(a), the waveform of the input signal applied to the delta-sigma modulator over time is presented. The input signal has a peak-to-peak voltage of 100 mV and a frequency characteristic of 50 Hz, with an input range set to 300 mV. Fig. 14(b) displays the output bitstream waveform corresponding to the input signal. In oversampling ADC, where more samples are collected and averaged to determine a single value, frequent repetitions of VDD and GND near the common-mode voltage occur, particularly challenging near the common-mode voltage where the difference between VINP and VINN is almost zero, as shown in Fig. 14(b). Fig. 15 shows the results of the fast Fourier transform (FFT) simulation for the fabricated second-order delta-sigma modulator. Coherent sampling techniques were employed for precise signal restoration. The sampling frequency (f$_{S}$) was set to 73.5 kHz, with 13 cycles for the input cycle, and the FFT point number was set to 16384 points. In this configuration, the input frequency is defined as in Eq. (1), as follows:

Utilizing the coherent sampling technique, the input frequency (f$_{IN}$) was set to 58.3191 Hz. The input signal had an amplitude of 100 mV$_{\mathrm{PP}}$, and the input range was configured to 500 mV. Employing a Hanning window resulted in a signal-to-noise ratio (SNR) of 82.6 dB and an effective number of bits (ENOB) of 13.4 bits for the designed second-order delta-sigma modulator.

Fig. 16 presents the measured input-output results of the fabricated second-order delta-sigma modulator. In (a), the waveform of the input signal (V$_{INP}$) applied to the fabricated second-order delta-sigma modulator is displayed. The input signal has a peak-to-peak voltage of 100 mV and a frequency characteristic of 50 Hz, consistent with the simulation conditions in Fig. 14. In (b), the output waveform of the fabricated second-order delta-sigma modulator is illustrated. When the input voltage is high, it tends to output more '1' bits, and when the input voltage is low, it tends to output more '0' bits. Additionally, when the input voltage is near the common-mode voltage, it outputs nearly an equal number of '1' and '0' bits.

Fig. 17 presents the power spectral density (PSD) measurement results of the fabricated second-order delta-sigma modulator in the frequency domain. For accurate measurements, the coherent sampling technique was applied to determine the input signal. The bandwidth of the second stage integrator is approximately 0.6 MHz. to ensure that the sampling clock signal satisfies a gain of at least 20 dB, preventing distortion in the sampling signal, the sampling frequency was set to 73.5 kHz, the input signal cycle was 13, and the FFT point count was 16384, resulting in an input frequency of 58.3191 Hz. Table 2 outlines various design parameters associated with the input frequency.

A peak-to-peak voltage of 30 mV$_{\mathrm{PP}}$ was applied as the input signal. Consequently, the peak value of the output signal is measured at -20 dBFS. The bandwidth of the fabricated second-order delta-sigma modulator can be calculated using the Eq. (2), as follows:

The proposed circuit was set to target signals less than 100 Hz, such as DC measurement like temperature sensor and bridge sensor, and low-frequency signals such as bio-sigmal sensors. The bandwidth of the delta-sigma modulator is determined by Eq. (2), so the OSR was set to 512 to satisfy the bandwidth less than 100 Hz. In other words, the bandwidth of the fabricated second-order delta-sigma modulator is 71.77 Hz. Additionally, the in-band noise bandwidth of the modulator is twice the modulator bandwidth, resulting in 143.55 Hz. The noise floor within the modulator's in-band is approximately -95 dB, and due to oversampling and noise shaping, low-frequency noise is pushed into the high-frequency band, resulting in a 40 dB/decade slope of noise shaping in the high-frequency band. At this point, the modulator's SNR is approximately 64 dB, ENOB is at the level of 10.3 bits.

Fig. 18 illustrates the SNR performance of the delta-sigma modulator based on the magnitude of the input signal. The input signal varies from -80 dBFS (30 ${\mu}$V$_{\mathrm{PP}}$) to 0 dBFS (300 mV$_{\mathrm{PP}}$), where 0 dBFS represents the maximum range of the input, which is 300 mV$_{\mathrm{PP}}$. The maximum SNR value of the fabricated second-order delta-sigma modulator is 76 dB, DR is 86 dB, and the ENOB is 12.3 bits.

Table 3 presents a performance comparison between the proposed second-order delta-sigma modulator circuit and existing research results. The proposed circuit demonstrates advantages in terms of power consumption and area. The figure-of-merit (FOM) provided in the Table 3 can be calculated using the Eq. (3), as follows:

Fig. 12. The chip photo of the fabricated circuit.

Fig. 13. The measurement setup of the fabricated delta-sigma modulator circuit.

Fig. 14. The transient simulation results of the fabricated circuit: (a) input signal; (b) output signal.

Fig. 15. The FFT simulation results of the fabricated circuit.

Fig. 16. The measurement results of the fabricated circuit: (a) input signal; (b) output signal.

Fig. 17. The FFT measurement results of the fabricated circuit.

Fig. 18. The measurement results of SNR according to input amplitude.

V. CONCLUSIONS

This paper introduces a second-order delta-sigma modulator circuit based on a differential difference amplifier without an input buffer. The proposed delta-sigma modulator, which eliminates the input buffer, effectively addresses area and power consumption concerns inherent in conventional delta-sigma modulators with input buffers. The circuit comprises two integrators for constructing the loop filter, a comparator for quantization, and additional sub-blocks. The first-stage integrator adopts a discrete-time differential difference amplifier structure, creating a high-impedance input stage by separating the paths of the input and feedback signals. The second-stage integrator features a discrete-time fully differential amplifier structure, utilizing a CMOS rail-to-rail input design and a gain-boosting amplifier circuit to amplify small input signals effectively. The comparator, composed of a preamp and latch, enhances quantization accuracy. Fabricated using the TSMC 0.18-${\mu}$m RFCMOS process, the circuit has an active area of 0.56 mm$^{2}$. By incorporating a differential difference amplifier input stage, this paper achieves high input impedance, reducing additional area and power consumption associated with input buffer removal. The proposed circuit attains a maximum SNR of 76 dB, and the ENOB is 12.3 bits. These findings suggest that the second-order delta-sigma modulator presented in this paper is well-suited for DC measurement and low-frequency signal conversion applications in ADCs.