AkuriNaga Ganesh1
JatothDeepak Naik2
KumarSandeep3,†
SongHanjung4
KarAsutosh5
-
(4Department of E&C Engg, National Institute of Technology Karnataka, Surathkal, Mangaluru,
India)
-
(Special Centre for Nanosciences, Jawaharlal Nehru University (JNU), New Delhi, India)
-
(3Department of NanoScience and Engineering, Centre for Nano Manufacturing, Inje University,
Gimhae 621-749, Korea)
-
(Department of Electronics and Communication Engineering, National Institute of Technology
Jalandhar, Punjab, India)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Front-end amplifier, low-pass filter, complementary metal oxide semiconductor (CMOS), bio-medical, neural system
I. INTRODUCTION
Nowadays, research in biomedical applications insists on new designs and techniques
with improved performance for neural monitoring wireless systems. An implantable neural
interface system records neural activity using multichannel electrodes and monitors
many human neurons [1,2]. However, this neural interface system should be in a small die area, with less noise
and ultra-low power consumption, ensuring no damage to the tissue. In several biomedical
applications, such as electrocardiogram, and electroencephalography biopotentials
are very low in both amplitudes and frequency.
Fig. 1 shows an implicit view of the human brain where the observable electrical activity
of neurons is minimal in amplitude and operates in the sub-Hz frequencies. It can
be further classified as an action potential value (AP) and a local field potential
value (LFP). Typically, AP's have a maximum peak-to-peak amplitude of 5 µV to 500
µV in the frequency range of 300 Hz to 7.0 kHz, whereas LFP's amplitude is around
1 mV down to 5 mV over the frequency range of 100 Hz to 25 MHz [3-5]. To perceive such signals, an efficient and robust high-performance front-end amplifier
(FEA) with low noise, high input impedance, and low power consumption with a lower
form factor is required [6].
In [7], a bio amplifier is employed, which uses off-chip capacitors in the order of nF,
in which the high-pass corner frequency (i.e., the minimum frequency at which FEA
can amplify sub-Hz biomedical potentials) is limited to 30 Hz only. Typically, implantable
devices dissipate power in the form of heat flux, which is around 80 mW/cm2 and which damages the sensitive muscle tissues; hence, less power dissipation became
an essential metric in biomedical applications [8]. An active electrode integrated circuit consumes a large power dissipation of 360
µW with an input impedance of 100 MΩ, while it is not suitable for implantability
[9]. A complementary input amplifier dissipates the considerable power dissipation of
12 µW and operates in the band of 0.05 Hz to 10.5 kHz [10]. FEA using an instrumentation amplifier provides different variable gains of (14,
20, 26, and 40 dB), according to requirement; however, the large form factor of 1.2
mm2 is the bottleneck to implantable devices [11]. In [12], the current feedback instrumentation amplifier uses a switched capacitor integrator
to suppress flicker noise, resulting in a high noise density of 64 ${\mathrm{nV} /
\sqrt{\mathrm{Hz}}}$. A bio-potential amplifier with a current mirror operational
transconductance amplifier (OTA) achieved a fine form factor of 0.22 mm2, which yielded less gain of 39.8 dB with a bandwidth of 30 Hz, bearing 21${\mathrm{nV}
/ \sqrt{\mathrm{Hz}}}$ of input-referred noise [13,14]. Moreover, the auto zeroing technique is commonly used in FEA to reduce the leakage
current and flicker noise to zero, which employs a two-state sample and hold technique
[15]. However, the equivalent input referred noise was achieved to be 79 µVrms. While
in [16], input referred noise was reduced to 4.98 µVrms in low power LNA, with high-pass
corner frequency limited to 10 mHz, with a lower input impedance of 16 MΩ at 1kHz.
Capacitive feedback techniques are used to increase input impedance up to 1.6 GΩ only,
with a power consumption of 2.8 µW [17]. A fixed value of a capacitor is used in the current compensation feedback (CCF)
to reduce the leakage current; thus the input current of FEA reduces, which boosts
the input impedance to 60 GΩ, with a less gain of 14 dB in the expense of 7.6 µW [18]. Bootstrapped FEA improves gain to 75 dB, with an improvement in input impedance
to 42 GΩ by reducing leakage current, but high-pass corner frequency restricted to
300 MHz. Its inherent input referred noise is achieved at 18.2 ${\mathrm{nV} / \sqrt{\mathrm{Hz}}}$
at 1 MHz where residing in the chip area of 0.042 mm2 at the expense of 3.1
${µW}$ [19]. In addition, [20] suggested the measurement results of MOSFETs, which showed an induced gate noise
that deviates from most of the models. Hence, it is necessary to reduce distributed
gate resistance which helps to attain ultra-low noise.
Therefore, in this work, the proposed FENA with LPF biasing technique and optimized
TULN-OTA helped to achieve an ultra-low noise design here that led to input referred
noise of 18 ${\mathrm{fV} / \sqrt{\mathrm{Hz}}}$, with a splendid gain of 80 dB. To
give more prominence to biomedical signals (as frequency lies in the order of mHz),
it sustains a high-pass corner of 1 mHz. In order to protect tissues from heat flux
issues, the proposed FENA dissipates a less power of 1 µW. The work is organized as
follows: Section 2 includes conventional FEA design and their trade-offs, while Section
3 includes a proposed FENA design using gm over id algorithm. And finally, Section
4 describes the results and discussion, followed by a conclusion in Section 5.
Fig. 1. Implicit view of the Human brain.
II. CONVENTIONAL FEA DESIGN
In this section, the design trade-off of conventional Front End Amplifier (FEA) will
be discussed.
1. Conventional FEA Design Trade-offs
A conventional FEA consists of two operational transconductance amplifiers (named
OTA1 and OTA2) with neutralisation current feedback (NCF) and voltage bootstrapping
(VB) techniques, which are shown in Fig. 2(a). To be elaborative, each OTA has a two-stage low noise amplifier (TLNA), as shown
in Fig. 2(b). The cumulative gain of two OTA's (OTA1 and OTA2) is 75 dB, which in turn increased
the input impedance to 42 GΩ (observed at 1kHz). The NCF and VB techniques are implemented
with the elements of three capacitors named as $C_{Neu,f}$, $C_{N}$ and $C_{B}$ and
three Pseudo resistors named $PR_{1}$ to $PR_{3}$. To achieve large input resistance
with an acceptable layout area, a Pseudo resistor was designed by the back-to-back
connection of the two Metal Oxide Semiconductor Field Effects (MOSFET's) [19].
Fig. 2. Conventional FEA with its: (a) Block schematic representation; (b) Full schematic view of TLNA.
In general, an FEA leakage current ($I_{leak}$ ) depends upon gate oxide capacitance
and the area (W and L) of the differential input stage in the TLNA. The leakage current
$I_{leak}$ of FEA is given by (1) [19].
where W and L are the width and length of the differential amplifier input stage MOSFET's,
$X=\frac{q^3}{16 \pi^2 h \varnothing_{o x}^{1.5}}, Y=-4 \pi \sqrt{ } 2 m_{o x} \varnothing_{o
x}^{1.5}$, h is Planck's constant, q is the electron charge, $t_{oxide}$ is the oxide
thickness, and $V_{oxide}$ is the gate oxide breakdown voltage, $m_{ox}$ is the
effective mass of tunnelling particle, $\varnothing_{ox}$ is the height of tunnelling
barrier. Here, the neutralisation of leakage current ($I_{leak}$ ) minimizes the input-referred
noise of the FEA. This compensation happens due to the applied neutralisation capacitor
$C_{Neu,f}$ in the current feedback path by$I_{Neu,f}$. The input current of FEA can
be expressed as in Eq. (2) [19].
From Eq. (2), it is realised that input current ($I_{in}$ ) was optimised, such that input referred
noise was reduced to 18.2 ${\mathrm{nV} / \sqrt{\mathrm{Hz}}}$ only at 1 KHz. In addition,
it is also observed with our research potential that each PMOS/NMOS with a large form
factor was employed in the conventional FEA (both OTA's). Due to this, the $R_{G}$
of corresponding MOSFET's increases, which results in high thermal noise by the amount
of $4kTR_{G}$ and the observation picture is shown in Fig. 3 [21]. The equivalent distributed gate resistance ($R_{G}$) can be expressed as in Eq.
(3).
Fig. 3. Equivalent circuit of distributed gate resistance.
In the current biasing circuit of a differential amplifier in the TLNA schematic,
current ($I_{pm4}$) replicating MOSFET $PM_{4}$ made twice the aspect ratio of the reference MOSFET $PM_{REF}$ to meet the required current. This reference bias current ($I_{bias}$ ) multiplication
by two times increases the flicker noise by the same amount in $I_{pm4}$. So, this
work derived the current noise spectrum of the $PM_{4}$, is enumerated by applying the superposition theorem to the individual noise spectrums
of , and as given in Eqs. (4) and (5).
As (W/L)$_{PM4}$=2(W/L)$_{PMref}$ , then =2, then Eq. (5) can be modified as in (6) and (7) resemble high current noise spectrum .
where , represent the output noise voltage spectrum of $PM_{REF}$ and $PM_{4}$, respectively.
is the input current noise spectrum of $PM_{4}$·g$_{PMref}$ , g$_{PM4}$ represents
transconductance of $PM_{REF}$ , and $PM_{4}$ respectively. The above derivation of
the noise current spectrum is formulated by considering the current replicating MOSFET's
($PM_{REF}$ , $PM_{4}$) and its noise equivalent sources, which are given in Fig. 4(a) and (b), respectively.
Fig. 4. Partial view of conventional FEA-bias current distribution network with (a) current replicating MOSFET’s $PM_{REF}$ and $PM_{4}$ ; (b) Noise equivalent sources of $PM_{REF}$ and $PM_{4}$.
It is clear from Fig. 4 that this increased noise component in the $I_{bias}$ propagates to the amplifier,
which corrupts the signal and degrades the performance of FEA. Moreover, it is also
perceived that the conventional FEA, VB technique not only reduces signal current
but also improved high-pass corner frequency and the input impedance of FEA (42 GΩ
at 1KHz). Sorting of node voltages $V_{out}$ ,$V_{in}$ and $V_{B}$ using the elements
OTA2, $C_{B}$, $PR_{2}$ and $PR_{1}$ in the VB. When $V_{B}$ approaching $V_{in}$
, the current through large $PR_{1}$ minimised subjected to the parasitic capacitance
($C_{p}$) across $PR_{1}$. The high-pass corner frequency is a function of $C_{B}$
and $PR_{2}$. Therefore, the minimum high-pass corner frequency of conventional FEA
obtained is 300 mHz. Hence, to attain infinitesimal noise, the input noise current
spectrum, , overall distribution resistance ($R_{G}$ ), and parasitic capacitance ($C_{p}$)
of FEA have to be minimized. Therefore, a noise elimination technique is proposed
here, that incurs the conventional design parameter trade-offs, which will be discussed
in the next section.
3. Proposed FENA Design and Optimization
Fig. 5 is shown the proposed schematic of FENA with incorporated techniques. The proposed
FENA consists of only a two-stage ultra-low noise operational transconductance amplifier
(TULN-OTA) operated with the proposed low-pass filter current biasing circuit. A TULN-OTA
has a differential mode topology named, $PM_{1}$,$PM_{2}$,$NM_{1}$ and $NM_{2}$ followed
by a common source amplifier named, $PM_{5?}$ and $NM_{5}$. Here, the current biasing
circuit consists of various dimensions named, $PM_{REF1}$,$PM_{REF2}$,$R_{LPF}$ ,$C_{LPF}$
,$NM_{3}$,$NM_{4}$,$PM_{3}$. and$PM_{4}$The resistance $R_{LPF}$ (constituting $PM_{LPF1}$,
$PM_{LPF2}$) and $C_{LPF}$ form low-pass filter design. A comprehensive noise performance
analysis is done to achieve an ultra-noise metric of 18 ${\mathrm{fV} / \sqrt{\mathrm{Hz}}}$
at 10 kHz with the proposed noise-free biasing current and optimum design of TULN-OTA.
TULN-OTA is designed in such a way that it yields the best high-pass corner frequency
(1 mHz) and noise by considering the operating input stage MOSFET's named as ($PM_{1}$,$PM_{2}$,$NM_{1}$,and$NM_{2}$)
in deep subthreshold region, and MOSFET's optimised using an appropriate number of
fingers too, using gm over id algorithm in section 3.2.
Fig. 5. Proposed FENA complete Schematic view.
1. Noise Optimization
The purity of biasing current plays a vital role in the noise metric. The bias current
multiplication requirement increases the flicker noise, and low-pass filter technique
designed by $R_{LPF}$ and $C_{LPF}$ avoids the same. From Eq. (7), it can be seen that the conventional bootstrapped FEA provides noise in the biasing
current (). For the proposed FENA, the optimum current noise spectrum () of MOSFET $PM_{4}$ is expressed as (8) to (13).
Here $R_{(lpf)}$ is the resistance seen from $PM_{LPF2}$ to $PM_{REF1}$. It is written
as (10) to (11)
Plugging Eq. (11) in (9) results the Eq. (12)
where , voltage noise spectrum of reference MOSFET. $g_{pmlpf2}$,g$_{PM4}$ represents transconductance
of $PM_{LPF2}$ and $PM_{4}$ respectively. $r_{pmpf1}$, $r_{pmpf2}$ are resistance
offered by $PM_{LPF1}$, and $PM_{LPF2}$ respectively. $C_{lpf}$ and w capacitance
of low-pass filter, and frequency in radians per second respectively. Here, voltage
noise spectrums of both $PM_{REF}$ are reduces by the factor of square of the LPF transfer function i.e. , thus results in a reduction in the noise current factor, . Here for the frequency range of 1 mHz to 10 kHz, before the low-pass filter noise
bias current, is in the order of 10-4 and after low-pass filter noise-free bias current, obtained is in the order of 10-18 to 10-24, as shown in Fig. 6.
Fig. 6. Comparison plot of noise spectrum of biasing current ($\overline{\mathrm{I}_{\mathrm{n}, \text { bias }}^2}$
) and biasing current $\overline{\mathrm{I}_{\mathrm{n}, \text { PM4 }}^2}$ ) vs. frequency.
Using the low-pass filter in the biasing circuit reduces the noise contribution of
each MOSFET ($PM_{REF1,2}$), $PM_{lpf1,2}$, $PM_{3,4,5}$,and $NM_{3,4,5}$) in the
biasing circuit. The spot noise analysis at 1 kHz gives 1.18610-8 V_rms for the proposed FEA. Here, the noise of biasing MOSFET's ($PM_{REF1,2}$),
$PM_{lpf1,2}$, $PM_{3,4,5}$,and $NM_{3,4,5}$) decreased to the order of 10-18, which is almost zero percent, and only input stage MOSFET's ($PM_{1}$,2 and$NM_{1,2}$)
contributing noise as shown in the pie-chart in Fig. 7.
Fig. 7. Noise Contribution pie-chart.
Moreover, properly sizing MOSFET's can reduce input-referred noise. In general, the
equivalent noise circuit of MOSFET has thermal noise , and flicker noise are uncorrelated to one another. Here, voltage noise spectrum is induced by gate-distributed resistance ($R_{G}$), current noise spectrum induced across the channel, and voltage noise spectrum is induced due to improper bonds at the Si-SiO2sub> interface of the MOSFET. Even though flicker noise is dominant in sub-Hz frequencies,
thermal noise is not ignoble in the comprehensive noise metric for the same frequency
range [22]. The side view of the MOSFET structure and its complete noise equivalent are shown
in Fig. 8(a) and (b), respectively.
Fig. 8. (a) Sideview representation of MOSFET; (b) the overall noise equivalent of a MOSFET.
The total noise spectrum of the MOSFET be expressed in
(14)
where $r_{o}$ represents the channel resistance of the MOSFET, it is observed that
increasing the transconductance of input-stage MOSFET's could suppress and thermal
noise. Here the operating input stage of MOSFET's $PM_{1}$,$PM_{2}$,$NM_{1}$,and$NM_{2}$
in the deep subthreshold region can increase the transconductance ($g_{m}$) of corresponding
MOSFETs. In the deep subthreshold, the MOSFET current $I_{DS}$ is exponentially dependent
on the gate-to-source voltage $V_{GS}$ ; thus, transconductance upon IDS ($g_{m}$/$I_{DS}$
) is higher in the deep subthreshold region than strong inversion. While in strong
inversion, $g_{m}$/$I_{DS}$ is dependent on $I_{DS}^{-0.5}$, but it is a fixed value
of q/mkT in deep sub-threshold region, where q is a charge of electron 1.6*10-19 C, k is Boltzmann constant, T is the absolute temperature and m=($gm_{b}$+gm )/gm
(here, $gm_{b}$ is transconductance parameter of body effect) [4]. Therefore, the gain of FEA upon D.C. power in deep subthreshold becomes very high
compared to strong inversion. Moreover, operating input stage MOSFETs in deep subthreshold
also decreases the high-pass corner frequency, which is achieved around to be 1 mHz.
Hence, increasing the gain of FENA can increase the input impedance ($Z_{in}$ ) with
the deferred output signal of 498.82 μS in the post-layout. Furthermore, the thermal
noise can be decreased by considering fingers to each of the MOSFET in FENA. It is
observed that fingers decrease to both gate-distributed resistance ($R_{G}$.), and
parasitic capacitance ($C_{p}$) of corresponding MOSFETs. Here, the finger width of
every transistor and an appropriate number of fingers are considered without affecting
other metrics using the gm over id algorithm. By doing so, gate parasitic capacitance
($C_{p}$) of the overall proposed FENA is minimum (in the order of fF), eventually
giving minimum leakage current (in the order of fA) for the common mode voltage range
of 0.4 V to 0.8 V in the post-layout, thus resulting significant improvement in noise
metric as shown in the plot of Fig. 9.
Fig. 9. Post layout result of parasitic capacitance and Leakage current versus common mode voltage.
2. Gm/Id Algorithm to Improve Noise-Metric
Miniaturization leads to including short channel effects and the performance metric
deviates from the superficial theoretical results. A flawless $g_{m}$/$I_{d}$ algorithm
needs to be adopted for submicron technologies [23]. The algorithm endorsed to attain ultra-low noise, which is very useful in monitoring
the electrical activities of neurons. Here, the comparison of $g_{m}$/$I_{d}$ with
regularized drain current ($I_{d}$ over aspect ratio) improved the noise metric. In
the proposed current biasing circuit RLPF is increased by fixing CLPF to 0.5 pF. Using
gm over id iterations algorithm, it is observed that RLPF is increased by decreasing
width and increasing gate length of $PM_{LPF1,2}$. Thus noise current factor, well controlled by RLPF and CLPF. This algorithm is also useful for deciding dimensions
to operate $PM_{1,2}$ in deep subthreshold and also administrates second stage. The
flowchart of the procedure to improve the noise metric is shown in Fig. 10.
Here Table 1 lists the dimensions of each device used in FENA.
Fig. 10. $g_{m}$/$I_{d}$ algorithm to improve noise metric.
Table 1. Dimensions of proposed FENA
|
Device
|
Size (M*W/L)
|
Number of Fingers
|
|
PMREF 1,2
|
4*7.5 μm / 2 μm
|
2
|
|
PM1,2
|
4*3.75 μm / 1 μm
|
2
|
|
PM3
|
8*7.5 μm / 2um
|
2
|
|
PM4,5
|
8*7.5 μm / 2 μm
|
4
|
|
PMLPF 1,2
|
1*160 nm / 3 μm
|
1
|
|
NM1,2
|
4*750 nm / 2 μm
|
2
|
|
NM3,4
|
4*250 nm / 1 μm
|
2
|
|
NM5
|
2*5 μm / 3 μm
|
4
|
|
CLPF
|
1*1.5 μm/ 0.8 μm
|
20
|
|
CM
|
1*1 μm/ 0.4 μm
|
10
|
3. Process Voltage Temperature (PVT) Variations
Here, the analysis of PVT variations using Monte-Carlo simulations is evaluated and
discussed. To match the input differential amplifier, inter digitized centroid layout
technique is applied to the input stage MOSFET's ($PM_{1}$ with $PM_{2}$ and $NM_{1}$
with $NM_{2}$) [21]. Both $PM_{1}$ and $PM_{2}$ have a multiplier value of 4, i.e., $PM_{1}$ has four
elements $PM_{11}$, $PM_{12}$,$PM_{13}$, and $PM_{14}$. Similarly $PM_{2}$ has four
elements from $PM_{21}$, $PM_{22}$,$PM_{23}$ and $PM_{24}$. In the inter-digitized
centroid layout, $PM_{1}$ elements, $PM_{11}$, and$PM_{12}$, are placed in the centre
with edges as $PM_{2}$ elements, while $PM_{21}$, and $PM_{22}$ as in row1. In row2,
$PM_{2}$ elements $PM_{23}$ and $PM_{24}$ are placed in the centre with edges as $PM_{1}$
elements while $PM_{13}$, and$PM_{14}$ as in row2 which is in Fig. 11, and the same is applied to $NM_{1}$ and $NM_{2}$.
By Monte-Carlo analysis, Process Voltage Temperature (PVT) variations are observed
for the gain (at three different temperatures 27℃, -40℃, and 125℃), bandwidth (27℃)
with 1000 samples (N). The mean (μ) of gains is 79.19 dB , 81.62 dB , and 74.21 dB
with standard deviation (σ) of 1.93, 4.38, and 0.7, respectively, which are shown
in Fig. 12(a) to (c), respectively. The mean (μ) of unity gain-bandwidth is 3.71 MΩ with a standard
deviation (σ) of 0.2 MΩ for the temperature of 27℃ as shown in Fig. 12(d). For the input-referred noise, Fast Fast (FF-Best case), Typical Typical (TT-Normal),
Slow Slow (SS-Worst case) corners analysis at -40℃, 27℃, and 125℃ with a varying supply
voltage of 1.08 V, 1.2 V and 1.32 V are executed. It is observed that the same type
of corners is coinciding with one another (i.e., all F.F. corners are overlapping),
the input-referred noise (${\mathrm{V} / \sqrt{\mathrm{Hz}}}$) values are 5.63 E-14, 1.87 E-14, 9.48 E-15 at 1KHz for the FF, TT and SS corners respectively, which are shown in Fig. 13.
Fig. 11. Inter-digitized centroid layout to PM1with PM2.
Fig. 12. PVT Variations with (a) Gain at 27°C; (b) Gain at -40°C; (c) Gain at 125°C; (d) Unity gain bandwidth at 27°C.
Fig. 13. PVT variations at extreme corners for input referred noise.
IV. RESULTS AND DISCUSSION
In this section, the performance evaluation of the FENA will be discussed. The FENA
design and its complete layout are made using 28 nm CMOS technology in cadence virtuoso
design tool. The microchip die photograph of the proposed FENA is shown in Fig. 14(a), which occupies a chip area of 0.0023 ㎟. While a measurement setup is shown in Fig. 14(b). The parameters such as input-referred noise, gain and input impedance are measured
using the equipment's such as Agilent dynamic signal analyser 35760A, Zurich instruments
MFIA impedance analyser, power supply Rigol DP1308A and Tektronix signal generator
AFG3252. The performance of FENA commences with a voltage gain, which is obtained
at about 60 dB in the measured scenario, while 80 dB in the post-layout simulation
as shown in Fig. 15. In the biasing circuit, MOSFET $PM_{REF}$ is placed in the centre, and remaining
biasing MOSFETs are placed around the same in the layout, ensuring even distribution
of bias current, operating transistors with high $g_{m}$/$I_{d}$, resulting in a splendid
gain of 80 dB but moderate unity gain bandwidth of 4 MHz in the post layout result,
which can be seen in Fig. 15. By adopting low-pass filter, reducing $R_{G}$, proposed FENA design achieves an
ultra-low noise of 18 ${\mathrm{fV} / \sqrt{\mathrm{Hz}}}$, input referred noise at
10 kHz, which is shown in Fig. 16. Moreover, the input impedance plot versus frequency is shown in Fig. 17. It is noticed that the proposed FENA provides post-layout input impedance value
($Z_{in}$) of 1.47 TΩ while the measured value of 0.2 TΩ in the sub-Hz frequencies.
Even after measured, the input impedance is too high. In bio signal detection, the
input impedance invariably forms a voltage divider in FENA therefore this ultra-high
input impedance could lower the attenuation caused by the interface with neural electrodes.
Arranging the biasing MOSFETs properly, later inter digitization of input stage together
increased the matching among MOSFETs to improve the linearity. Fig. 18 shows total harmonic distortion (THD) vs frequency characteristics, with ten harmonics
of a sine wave for an input of 1mVpp at 1 kHz, and THD?is achieved as -68 dB. Operating
in subthreshold, high gm/ID provided optimum power supply rejection ratio (PSRR) of
the proposed FENA is approximately 95 dB and 80 dB for simulated and Post layout results,
respectively, as depicted below in Fig. 19. In addition, the noise efficient factor (NEF) for the FENA is expressed as (20).
where $V_{in,rms}$ is the input-referred noise in RMS (root mean square), $I_{bias}$
total biasing current, K is Boltzmann constant, T is Temperature,$V_{T?}$ is the thermal
voltage, and B.W is the bandwidth of the FENA. As this FENA can provide less input-referred
noise, NEF values improved to 0.09 and 0.27 for the AP (300 Hz to 7.5 KHz), LFP (25
mHz to 100 Hz), respectively. The comparison of the proposed FENA with other referred
ones is shown in Table 2 (Post-layout results). Even though this FENA competes with others in most of the
metrics, however moderate unity gain bandwidth of 4 MHz and the deferred output signal
of 498.82 μS is observed in the post-layout.
Table 2. Performance comparison of proposed FENA’s with other works
|
Parameter / FENA's
|
[18]
|
[10]
|
[16]a
|
[19]
|
[24]a
|
[12]
|
This work
|
|
Technology
|
0.18 CMOS
|
0.13
CMOS
|
0.18 CMOS
|
0.35
CMOS
|
0.18
CMOS
|
0.13
CMOS
|
28
CMOS
|
|
Biasing Technique
|
CCF
|
CA
|
FL
|
NCF
|
Tunable Bandwidth
|
Chopper Stabilization
|
LPF
|
|
Chip area
(mm2)
|
0.025
|
0.072
|
-
|
0.042
|
0.048
|
-
|
0.0023
|
|
Supply voltage (V)
|
1.8
|
1
|
0.6
|
3.3
|
1
|
1
|
1
|
|
Power (mW)
|
7.6
|
12.1
|
0.72
|
3.1
|
3.6
|
2.3
|
1
|
|
Input Referred
Noise (${\mathrm{V} / \sqrt{\mathrm{Hz}}}$)
|
5.6
|
2
|
1
|
18.2
(at 1 KHz)
|
2.1
|
64n
|
35
(at 1 kHz)
|
|
Gain (dB)
|
14
|
40
|
40
|
75
|
45-55
|
55
|
80
|
|
Bandwidth (Hz)
|
23
|
10.5
|
10
|
22.8 (Gain=0)
|
8.2
|
1.1
|
4
(Gain=0)
1.2 K
|
|
Input Impedance (W)
|
60
|
4
|
16
|
42
|
-
|
-
|
0.2 T
|
|
CMRR (dB)
|
61
|
-
|
77
|
-
|
98.28
|
115 to 125
|
77
|
|
PSRR (dB)
|
57
|
-
|
60
|
-
|
92.48
|
-
|
80
|
|
THD (dB)
|
< 1
|
-
|
75
|
-
|
-46.32
|
-
|
-68
|
|
Noise Efficiency Factor : AP
|
4.7
|
-
|
2.13
|
-
|
1.7
|
3.8
|
0.09
|
|
Noise Efficiency Factor : LFP
|
9.6
|
-
|
2.13
|
-
|
1.7
|
3.8
|
0.27
|
|
High-pass corner
Frequency (Hz)
|
0.01
|
-
|
10 m
|
300 m
|
0.8
|
0.1
|
1 m
|
Fig. 14. Proposed FENA circuit with its: (a) Microchip die photograph; (b) Prototype setup.
Fig. 15. Gain vs Frequency.
Fig. 16. Post layout and measured input-referred voltage noise.
Fig. 17. Input impedance of the proposed FENA.
Fig. 18. Harmonic distortion of the proposed FENA for 1 mVpp input.
Fig. 19. Post layout result of PSRR of the proposed FEA.
V. CONCLUSIONS
In this paper, proposed FENA with an LPF has been proposed, which occupies less area
of 0.0023 mm2, which increases the feasibility of implantable and wearable neuro-sensing devices.
The gm over Id algorithm is endorsed to attain noise-free biasing current, and TULN-OTA
yields ultra-low noise of 18 ${\mathrm{fV} / \sqrt{\mathrm{Hz}}}$ input referred noise
at 10 kHz, which is very much useful in monitoring the electrical activities of neurons.
This can achieve an input impedance of 0.2 TΩ at 1mHz while consuming 1 µW of power.
The inter digitized centroid layout not only decreases leakage current but also ensures
FENA, matching the input stage differential amplifier. FENA able to provides a splendid
post-layout gain of 80 dB, which is very useful for bio-medical low potentials with
moderate unity gain bandwidth of 4 Hz and deferred output signal of 498.82 μS.
ACKNOWLEDGMENTS
This research was supported by the part of India-Korea Research International
Bilateral Cooperation Division through the Ministry of Science and Technology, Government
of India under Grant (No. INT/Korea/P-55) and in part by the KOREA-INDIA joint program
of cooperation in science and technology through the National Research Foundation
of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2020K1A3A1A19086889).
Data availability: The datasets generated and/or analysed during the current study
are available from the corresponding author on reasonable request.
Conflict of Interest: There is no conflict of interest
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NAGA GANESH AKURI received a B.Tech in electronics and communication engineering
from JNTU Kakinda in 2011. He received an M.Tech degree in VLSI Systems from the National
Institute of Technology, Trichy (NITT) in 2014. He is pursuing a Ph.D. from the National
Institute of Technology, Karnataka (NITK). His research interests include the Ultra-low
noise neural Amplifier, Gaussian pulse generator, Modulator and Low noise amplifier
in CMOS Analog RF IC Design.
JATOTH DEEPAK NAIK received the B.Tech. degree in Electrical and Electronics Engineering
from the Jawaharlal Nehru Technological University Hyderabad, India, in 2014 and M.Tech.
degree in VLSI design from NITK Surathkal, India, in 2020. He is currently pursuing
the Ph.D. degree with Inje University, South Korea. His current research interests
include analog/RFIC circuit design transceiver system design, such as LNA, power amplifier,
and microwave passive devices circuit design.
Sandeep Kumar received a B.E. from Dr. B R Ambedkar State Government University,
Uttar Pradesh in 2008 and an M. Tech. from Gautam Buddha University, Uttar Pradesh
in 2012. He received his Ph.D. in Electronics Engineering from Indian Institute of
Technology (IIT), Dhanbad, Jharkhand in 2016 and Post-doctorate in Nano circuit design
from Inje University, South Korea. He is an Assistant Professor in the Department
of Electronics and communication engineering at NIT Karnataka Surathkal, India. .His
research interests include RF CMOS Integrated and Circuits, Analog Mixed signal circuit,
Optical transceiver, Electromagnetic sensors, Wireless communication, RF Amplifiers.
He has published more than 50 publications including 28 international SCI journals,
22 international conferences and several book chapters in IEEE, IET publishers etc.
Hanjung song was born in South Korea. He received his B.S, M.S and PhD degree in
Electronics Engi-neering from Hanyang University, Korea India in the year of 1986,
1988 and 2000 respectively. He joined Nano design circuit laboratory, Inje University,
South Korea in 2004 where he is currently as a Head and Professor in the department
of Nanoscience engineering. He has published several research papers in referred International
Journals. He is carrying out three sponsored research project as Principal Investigator.
His research interest includes power IC circuit design, analog RF VLSI design, Semiconductor
device modeling and reliability.
Ashutosh Kar is a Associate Professor in the Department of Electronics & Communication
Engineering at Dr B R Ambedkar NIT Jalandhar, Punjab, India. Earlier, He worked as
an Assistant Professor (Grade-I) in IIITDM Kancheepuram for nearly 4.8 years, BITS
Pilani, India [Pilani & Hyd. campus] for nearly 2 years. He was recipient of the Marie-Curie
Post-Doctoral fellowship at Aalborg University, Denmark from 2015 to 2017. He was
the visiting research scientist to ESAT lab at the Dept. of Electrical Engineering
at KU-Leuven, Belgium, and Dept. of Medical Physics and Acoustics at the University
of Oldenburg, Germany. His research field includes the areas of advanced digital signal
processing, adaptive filters, acoustics, machine learning, speech & image processing,
and hearing-aid system designs, communication systems.