1. Effect of Transition Density on CDR Behavior

CDR circuits have two trade-offs through the loop bandwidth (BW). The first is a trade-off between voltage-controlled oscillator (VCO) phase noise and pattern-dependent jitter, and the second is a trade-off between jitter tolerance and pattern-dependent jitter. To appreciate this point, let us write the bandwidth of a type-Ⅱ CDR as

where $\omega _{-3\mathrm{dB}}$, ${\zeta}$, and $\omega _{\mathrm{n}}$ are the 3-dB bandwidth, the damping factor, and the natural frequency. If $\zeta ^{2}\gg 1$, we have

where R, I$_{\mathrm{CP}}$, D$_{\mathrm{T}}$, and K$_{\mathrm{VCO}}$ are the loop filter resistor, the charge pump (CP) current, the transition density, and the VCO gain. By increasing the loop BW, VCO phase noise is suppressed, and jitter tolerance are improved. In Eq. (2), increasing the CP current or the VCO gain can enlarge the loop BW. However, pattern dependent jitter is proportional to CP imperfection and VCO gain. So, increasing the loop BW by raising the CP current or the VCO gain is disadvantageous for pattern-dependent jitter.

In Eq. (2), it is observed that a transition density is proportional to loop BW. In other words, great transition density allows a wider loop BW. To overcome the CDR tradeoffs, increasing the transition density is a good alternative for wider loop BW. Unlike increasing the CP current or the VCO gain, dealing with the transition density can increase the loop BW while suppressing the pattern-dependent jitter ^[9].

Furthermore, high transition density also reduces the droop in the loop filter’s voltage in the absence of data transitions, resulting in the deterministic jitter being reduced ^[9].

2. Correlation between the Number of Error Samplers and Loop BW in Baud-rate CDR

To design a SS-MMPD, which is commonly used in baud-rate CDR, additional error samplers are required for phase detection. Fig. 1 shows the utilization of samplers in the PAM-4 SS-MMPD. For conventional design, three data samplers and two error samplers are required. When using two error samplers, transition density is 0.125(=2/4$^{2}$). However, the addition of the error samplers leads to high power consumption because it limits the bandwidth of the AFE.

For an energy efficient design, the number of error samplers can be reduced. However, the absence of the error samplers leads to less transitions that the PD receives in unit time, resulting in narrow loop BW. In other words, there is a trade-off between the number of error samplers and loop BW. To design optimal PAM-4 baud-rate CDR, robust jitter tracking performance with a small number of error samplers is required ^[6-8].

Fig. 1. Sampler utilization in conventional PAM-4 SS-MMPD.

1. Sampler Utilization

The shared sampler method is that one sampler output is used for both data decoding and phase detection. In other words, a single sampler serves as both a data sampler and an error sampler simultaneously. Fig. 3 shows the sampler utilization in the shared sampler method. Four samplers and four reference voltages (REF3, REF2, REF1, REF0) are used. The voltage level corresponding to the PAM-4 data level is used as the reference voltage. In the shared sampler method, phase error information is extracted based on four levels, so PD can detect many transitions. Also, since no additional samplers are needed to decode the data, only four samplers per UI are required. Specific operation principle is described in the following paragraphs.

Fig. 3. Sampler utilization in shared sampler method.

2. Data Decoding Method (Data Sampler)

In shared sampler method, time-based decoder is used for data decoding. Fig. 4 shows the schematic of a time-based decoder. The time-based decoder utilizes the principle that the larger the input voltage difference of the sampler, the shorter the clock-q delay ^[8,10].

Fig. 4. Schematic of time-based decoder.

Operation principle of the time-based decoder is organized in Fig. 5. First, when the clock is low, the TB$_{P}$ node and the TB$_{N}$ nodes are pre-charged. Next, when the clock is high, the outputs of the two samplers are delivered as input and the clock-q delay is compared. Let the inputs of the time-based decoder be A$_{P}$/A$_{N}$ and B$_{P}$/B$_{N}$, respectively. If B$_{P}$/B$_{N}$ arrives before A$_{P}$/A$_{N}$, TB$_{N}$ starts discharging faster than TB$_{P}$ and is regenerated by the cross-coupled latch. As a result, TB$_{P}$ outputs ‘1’ and TB$_{N}$ outputs ‘0’. Conversely, if the B$_{P}$/B$_{N}$ arrives later than the A$_{P}$/A$_{N}$, the TB$_{P}$ outputs ‘0’ and the TB$_{N}$ outputs ‘1’. The inverted sampler outputs are passed through the time-based decoder for robust signal delivery.

Fig. 5. Operation principle of time-based decoder.

Fig. 6 is the block diagram of the proposed sampler and time-based decoder block. The input signal is sampled by four samplers that use the PAM-4 data level (REF3, REF2, REF1, REF0) as the threshold voltage. The output of the sampler is passed through two paths. First, it is passed to the phase detection path to extract the error of the clock phase. How to extract the timing error of the clock phase will be described in more detail in Ⅳ-3. At the same time, it is passed to the data recovery path for data decoding. Three pairs of sampler outputs using two adjacent threshold voltages (I$_{R3}$/I$_{R2}$, I$_{R2}$/I$_{R1}$, I$_{R1}$/I$_{R0}$) are passed to the time-based decoder, respectively. Each time-based decoder outputs a TB signal by comparing the clock-q delay of the samplers.

Fig. 6. Block diagram of samplers and time-based decoders.

Table 1 is the time-based decoder output according to input voltage difference. Defining 1 LSB difference as 1${\times}$, the voltage differences between input signal and threshold voltage are listed. For example, if input data=+1, the voltage differences between input data and reference voltage (REF3, REF2, REF1, REF0) are 1${\times}$, 0${\times}$, 1${\times}$, 2${\times}$, respectively. The output pairs of the sampler compared to the neighboring reference voltage (1${\times}$/0${\times}$, 0${\times}$/1${\times}$, 1${\times}$/2${\times}$) are passed to the time-based decoder. TB$_{32}$ outputs 0 because A$_{P}$/A$_{N}$ arrives first in the case of 1${\times}$/0${\times}$, and TB$_{21}$and TB$_{10}$ outputs 1 because B$_{P}$/B$_{N}$ arrives first in the remaining cases (0${\times}$/1${\times}$, 1${\times}$/2${\times}$). As a result, the output of the decoded data through the data recovery path is 011. In this way, PAM-4 signal is decoded by the proposed data decoding method.

However, the time-based decoder is affected by the nonlinearity of the sampler delay ^[10,11]. Fig. 7 shows the simulation results of clock-q delay versus input amplitude. The delay decreases nonlinearly as the input amplitude increases. Because time-based decoders operate by comparing clock-q delays, they are vulnerable to comparisons between small delays. In particular, the sensitivity of time-based decoder becomes more important due to various noises including device noise or input offset of time-based decoder. To overcome this problem, error correction block is proposed.

Fig. 7. Sampler clock-q delay versus input amplitude.

In the proposed decoding method, the case most affected by nonlinearity is when comparing sampler outputs with an input voltage difference of 2${\times}$ and 3${\times}$. In Table 1. the PAM-4 data most affected by the nonlinearity are +3 and -3. Each case involves comparing the clock-q delay when the sampler's input voltage difference is 2${\times}$ and 3${\times}$. If the time-based decoder outputs an incorrect value, it could output 110 when the input data is +3, and 100 when it is -3. To overcome the clock-q delay nonlinearity, an error correction block is proposed. The error correction block is a circuit that corrects the incorrect time-based decoder output signal. A 110 output indicates that the input data is +3, and a 100 output indicates that the input data is -3. By correcting the error to match the corresponding data, the clock-q delay nonlinearity of the sampler can be overcome. Fig. 8 shows the error correction block. It outputs 111 when the TB signal is 110, and outputs 000 when the TB signal is 100. To summarize, the time-based decoder can overcome the comparison when the input voltage difference is 2${\times}$ and 3${\times}$. Therefore, the timing margin of the difference of sampler delay has been increased and the sensitivity of the time-based decoder has been improved.

Fig. 8. Block diagram of error correction block.

3. Phase Detecting Method (Error Sampler)

The proposed PD utilizes pattern-based PD. Pattern-based PD is a PD that performs phase detection based on consecutive data patterns. The proposed PD determines the early/late of the clock based on three consecutive data.

Fig. 9 shows the operation principle of the proposed PD. The current data determines which reference voltage to use. And the PD determines the early/late of the clock phase according to the current error(e[n]) based on reference voltage. For example, if the current data(d[n]) is +3, the phase information is extracted using the sign of e$_{3}$[n] relative to REF3. For a monotonically increasing pattern, if the clock is early, e[n] outputs ‘-1’ because e[n] is low compared to the reference voltage. And if it is late, e[n] outputs ‘+1’ because e[n] is higher. Conversely, if the clock is early, e[n] outputs ‘+1’, and if it is late, e[n] outputs ‘-1’.

Fig. 9. Operation principle of proposed phase detector.

All the data patterns used in proposed PD is listed in Fig. 10 and Table 2. Only monotone increasing or monotone decreasing data patterns are employed. The reason for choosing the data patterns is as follows: The dominant first pre- (h$_{-1}$) and post-cursor (h$_{+1}$) ISI are considered. If both cursors are the same size (h$_{-1}$=h$_{+1}$), the data patterns whose sum of the pre-cursors and post-cursors in d[n] is either 0 or ${\pm2h}_{-1}$(or ${\pm2h}_{+1}$) are used. Because data patterns less affected by ISI are used, CDR lock point fluctuation is minimized. The proposed PD uses 24 data patterns, and the transition density is 0.375 (=24/4$^{3}$).

Fig. 10. Data patterns used in proposed PD: (a) Pure monotone; (b) Monotone and stay; (c) Stay and monotone.

Fig. 11 is the timing diagram of the proposed PD. First, PD identifies the data pattern based on three consecutive data. And it determines whether it is the pattern used by the proposed PD and whether it is a rising or falling pattern. If the data pattern belongs to one of the 24 cases, it determines the early/late based on the rising/falling information and error. Since the data pattern judgment is completed based on d[n+1], early/late is determined using retimed e[n].

Fig. 11. Timing diagram of proposed phase detector.

1. Simulation of Consecutive Bit Responses

To verify the receiver with proposed CDR, the entire block was designed and simulated in 65 nm CMOS process. All simulations have been done with post-layout. In addition, an FR4 type 210 mm channel was used.

Fig. 12 shows the simulation setup to check three consecutive bit responses of the PAM-4 signal after passing through the channel and CTLE. Fig. 13 is the simulated three consecutive bit responses of all cases that three consecutive PAM-4 signals can produce. The blue lines are the data patterns used by the proposed PD, and the black lines are the data patterns not used. And the red line indicates the level of the reference voltage. Simulations show that unused data patterns either do not pass through the reference voltage level or meet far from the ideal sampling phase. This can cause the CDR lock point to fluctuate and increase the clock jitter. On the other hand, the data patterns used by the proposed PD meet the reference voltage level in a narrow range, which reduces the fluctuation of the lock point while ensuring transition density. Fig. 14 is an eye diagram of the measured CDR. It has a peak-to-peak jitter of 9.35 ps, which is the proof that lock point is less fluctuated.

Fig. 12. The simulated SBR of channel with CTLE and test setup for three consecutive bit responses.

Fig. 13. Simulation of three consecutive bit responses.

Fig. 14. Eye diagram of (a) equalized data; (b) recovered clock (3.125 GHz) for 10,000 UI samples.

2. Simulation of Jitter Tolerance

To verify the transition density and loop BW, a simulation of jitter tolerance is performed. Fig. 15 shows the test setup for jitter tolerance simulation. To increase the reliability of the verification, a noise environment was considered. The noises considered are as follows: ① TX clock jitter (RJ+SJ) ② Reference voltage noise ③ VCO phase noise. To simulate jitter tolerance, a sinusoidal jitter source is used to generate the input signal at the TX clock. The maximum jitter amplitude that can be tolerated per frequency is simulated by increasing the jitter amplitude until reaching the threshold BER at each jitter frequency.

Fig. 15. Test bench for jitter tolerance simulation.

To verify the improved jitter tolerance, proposed CDR and conventional PAM-4 baud-rate CDR which employs SS-MMPD are compared. All blocks except the PD and Decoder block were designed the same to enable jitter tolerance comparison based solely on phase detecting performance. Fig. 16 shows the jitter tolerance comparison. Proposed CDR has most improved jitter tolerance in all the jitter frequency and has wide loop BW. The conventional CDR using SS-MMPD has a transition density of 0.125, while the proposed CDR has a transition density of 0.375. Therefore, the proposed CDR has a wider loop bandwidth and better jitter tolerance.

Fig. 16. Simulation result of jitter tolerance.

3. Power Consumption

The proposed 25-Gbps PAM-4 receiver consumes 19.6~mW of power at a supply voltage of 1.2 V. Fig. 17 shows the power breakdown of the proposed PAM-4 receiver. And Table 3. shows the performance comparison between this paper and other PAM-4 receivers using baud-rate CDR. The proposed CDR has a high transition density and low power consumption compared to other receivers.

Fig. 17. Power breakdown of proposed receiver.