ChoSeoung-Geun1
KangJin-Ku1
-
(System Integrated Circuit Design Lab, Inha University, 100, Inha-ro, Michuhol-gu,
Incheon 22212, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
CMOS, high-speed, PAM-4 receiver, baud-rate CDR, time-domain, jitter tolerance, transition density
I. INTRODUCTION
As emerging technologies such as AI and autonomous vehicles become prevalent, the
demand for high-speed interfaces has increased. However, the channel bandwidth limits
the transmission of high data rate signals. To satisfy the limited bandwidth, PAM-4
signaling has been used instead of Non-Return to Zero (NRZ) signaling. However, multi-level
signaling reduces the vertical eye-opening margin compared to NRZ, causing signal-to-noise
ratio (SNR) degradation. So, to obtain low bit error rate (BER), the improved CDR
design is required [1-9].
In the early PAM-4 CDRs, 2x-oversampling CDR is employed for their simplicity. However,
it requires an extra clock phase for edge sampling, resulting in high power consumption
[1-3, 9]. Meanwhile, a baud-rate CDR has drawn attention because it requires only
one clock phase per UI. The Mueller-M\"{u}eller phase detector (MM-PD), which is commonly
used in baud-rate CDRs, requires analog-to-digital converter (ADC). However, high-speed
and high-resolution ADCs result in high power consumption and increase hardware complexity.
For simplicity, a sign-sign MMPD (SS-MMPD) was presented. The SS-MMPD for PAM-4 signaling
requires two or more error samplers per UI for phase detection as well as data samplers
for data decoding [4-8].
However, in multi-phase architecture, the additional sampler leads to the burden of
clock buffer and analog front-end (AFE). PAM-4 baud-rate CDRs are proposed to reduce
the number of samplers, but still have great jitter characteristics [6-8]. In [7], the total number of samplers is reduced to four per UI by using only one error sampler.
In addition, a transition weighted PD is proposed to perform different detection behavior
considering the transition type of the PAM-4 signal. However, it requires additional
hardware and high-power consumption. In [8], the number of samplers is reduced to four per UI by using two error samplers and
two data samplers. And a pattern-based PD is employed to overcome the degradation
of phase detecting performance due to ISI. However, it still has a low transition
density (0.125).
In this paper, a PAM-4 baud rate CDR with high jitter tolerance is proposed. A sampler
performs the roles of data sampler and error sampler simultaneously by using shared
sampler method. So, only four samplers are utilized per UI, resulting in energy efficient
CDR design. In addition, it has a high transition density (0.375) because all the
samplers act as error sampler. Furthermore, the proposed PD determines the phase error
based on three consecutive data resulting in the CDR lock point fluctuation being
minimized.
This paper is organized as follows: Section Ⅱ provides the background for this work.
Section Ⅲ describes the architecture of the proposed CDR. Section Ⅳ explains about
a shared sampler method. Section Ⅴ presents the simulation results and comparison
to the recently reported PAM-4 baud-rate CDRs. Section Ⅵ concludes this paper.
II. BACKGROUND
1. Effect of Transition Density on CDR Behavior
CDR circuits have two trade-offs through the loop bandwidth (BW). The first is a trade-off
between voltage-controlled oscillator (VCO) phase noise and pattern-dependent jitter,
and the second is a trade-off between jitter tolerance and pattern-dependent jitter.
To appreciate this point, let us write the bandwidth of a type-Ⅱ CDR as
where $\omega _{-3\mathrm{dB}}$, ${\zeta}$, and $\omega _{\mathrm{n}}$ are the 3-dB
bandwidth, the damping factor, and the natural frequency. If $\zeta ^{2}\gg 1$, we
have
where R, I$_{\mathrm{CP}}$, D$_{\mathrm{T}}$, and K$_{\mathrm{VCO}}$ are the loop
filter resistor, the charge pump (CP) current, the transition density, and the VCO
gain. By increasing the loop BW, VCO phase noise is suppressed, and jitter tolerance
are improved. In Eq. (2), increasing the CP current or the VCO gain can enlarge the loop BW. However, pattern
dependent jitter is proportional to CP imperfection and VCO gain. So, increasing the
loop BW by raising the CP current or the VCO gain is disadvantageous for pattern-dependent
jitter.
In Eq. (2), it is observed that a transition density is proportional to loop BW. In other words,
great transition density allows a wider loop BW. To overcome the CDR tradeoffs, increasing
the transition density is a good alternative for wider loop BW. Unlike increasing
the CP current or the VCO gain, dealing with the transition density can increase the
loop BW while suppressing the pattern-dependent jitter [9].
Furthermore, high transition density also reduces the droop in the loop filter’s voltage
in the absence of data transitions, resulting in the deterministic jitter being reduced
[9].
2. Correlation between the Number of Error Samplers and Loop BW in Baud-rate CDR
To design a SS-MMPD, which is commonly used in baud-rate CDR, additional error samplers
are required for phase detection. Fig. 1 shows the utilization of samplers in the PAM-4 SS-MMPD. For conventional design,
three data samplers and two error samplers are required. When using two error samplers,
transition density is 0.125(=2/4$^{2}$). However, the addition of the error samplers
leads to high power consumption because it limits the bandwidth of the AFE.
For an energy efficient design, the number of error samplers can be reduced. However,
the absence of the error samplers leads to less transitions that the PD receives in
unit time, resulting in narrow loop BW. In other words, there is a trade-off between
the number of error samplers and loop BW. To design optimal PAM-4 baud-rate CDR, robust
jitter tracking performance with a small number of error samplers is required [6-8].
Fig. 1. Sampler utilization in conventional PAM-4 SS-MMPD.
III. ARCHITECTURE
Fig. 2 shows the top block diagram of a PAM-4 receiver employing proposed baud-rate CDR.
To reduce the timing constraints, quarter-rate clocking is employed. The 25-Gbps PAM-4
signal which passed through the channel is equalized by continuous time linear equalizer
(CTLE) with a boost-up to 8.1dB at Nyquist frequency. The amplified signal by a variable-gain
amplifier (VGA) is sampled by samplers. The data signals and error signals generated
by the sampler and time-based decoder are passed to the pattern-based PD. The pattern-based
PD uses the data and error information to determine the early/late of the clock. The
architecture is designed as a PLL-based CDR structure.
Fig. 2. Top block diagram of proposed PAM-4 receiver.
IV. SHARED SAMPLER METHOD
1. Sampler Utilization
The shared sampler method is that one sampler output is used for both data decoding
and phase detection. In other words, a single sampler serves as both a data sampler
and an error sampler simultaneously. Fig. 3 shows the sampler utilization in the shared sampler method. Four samplers and four
reference voltages (REF3, REF2, REF1, REF0) are used. The voltage level corresponding
to the PAM-4 data level is used as the reference voltage. In the shared sampler method,
phase error information is extracted based on four levels, so PD can detect many transitions.
Also, since no additional samplers are needed to decode the data, only four samplers
per UI are required. Specific operation principle is described in the following paragraphs.
Fig. 3. Sampler utilization in shared sampler method.
2. Data Decoding Method (Data Sampler)
In shared sampler method, time-based decoder is used for data decoding. Fig. 4 shows the schematic of a time-based decoder. The time-based decoder utilizes the
principle that the larger the input voltage difference of the sampler, the shorter
the clock-q delay [8,10].
Fig. 4. Schematic of time-based decoder.
Operation principle of the time-based decoder is organized in Fig. 5. First, when the clock is low, the TB$_{P}$ node and the TB$_{N}$ nodes are pre-charged.
Next, when the clock is high, the outputs of the two samplers are delivered as input
and the clock-q delay is compared. Let the inputs of the time-based decoder be A$_{P}$/A$_{N}$
and B$_{P}$/B$_{N}$, respectively. If B$_{P}$/B$_{N}$ arrives before A$_{P}$/A$_{N}$,
TB$_{N}$ starts discharging faster than TB$_{P}$ and is regenerated by the cross-coupled
latch. As a result, TB$_{P}$ outputs ‘1’ and TB$_{N}$ outputs ‘0’. Conversely, if
the B$_{P}$/B$_{N}$ arrives later than the A$_{P}$/A$_{N}$, the TB$_{P}$ outputs ‘0’
and the TB$_{N}$ outputs ‘1’. The inverted sampler outputs are passed through the
time-based decoder for robust signal delivery.
Fig. 5. Operation principle of time-based decoder.
Fig. 6 is the block diagram of the proposed sampler and time-based decoder block. The input
signal is sampled by four samplers that use the PAM-4 data level (REF3, REF2, REF1,
REF0) as the threshold voltage. The output of the sampler is passed through two paths.
First, it is passed to the phase detection path to extract the error of the clock
phase. How to extract the timing error of the clock phase will be described in more
detail in Ⅳ-3. At the same time, it is passed to the data recovery path for data decoding.
Three pairs of sampler outputs using two adjacent threshold voltages (I$_{R3}$/I$_{R2}$,
I$_{R2}$/I$_{R1}$, I$_{R1}$/I$_{R0}$) are passed to the time-based decoder, respectively.
Each time-based decoder outputs a TB signal by comparing the clock-q delay of the
samplers.
Fig. 6. Block diagram of samplers and time-based decoders.
Table 1 is the time-based decoder output according to input voltage difference. Defining
1 LSB difference as 1${\times}$, the voltage differences between input signal and
threshold voltage are listed. For example, if input data=+1, the voltage differences
between input data and reference voltage (REF3, REF2, REF1, REF0) are 1${\times}$,
0${\times}$, 1${\times}$, 2${\times}$, respectively. The output pairs of the sampler
compared to the neighboring reference voltage (1${\times}$/0${\times}$, 0${\times}$/1${\times}$,
1${\times}$/2${\times}$) are passed to the time-based decoder. TB$_{32}$ outputs 0
because A$_{P}$/A$_{N}$ arrives first in the case of 1${\times}$/0${\times}$, and
TB$_{21}$and TB$_{10}$ outputs 1 because B$_{P}$/B$_{N}$ arrives first in the remaining
cases (0${\times}$/1${\times}$, 1${\times}$/2${\times}$). As a result, the output
of the decoded data through the data recovery path is 011. In this way, PAM-4 signal
is decoded by the proposed data decoding method.
However, the time-based decoder is affected by the nonlinearity of the sampler delay
[10,11]. Fig. 7 shows the simulation results of clock-q delay versus input amplitude. The delay decreases
nonlinearly as the input amplitude increases. Because time-based decoders operate
by comparing clock-q delays, they are vulnerable to comparisons between small delays.
In particular, the sensitivity of time-based decoder becomes more important due to
various noises including device noise or input offset of time-based decoder. To overcome
this problem, error correction block is proposed.
Fig. 7. Sampler clock-q delay versus input amplitude.
In the proposed decoding method, the case most affected by nonlinearity is when comparing
sampler outputs with an input voltage difference of 2${\times}$ and 3${\times}$. In
Table 1. the PAM-4 data most affected by the nonlinearity are +3 and -3. Each case involves
comparing the clock-q delay when the sampler's input voltage difference is 2${\times}$
and 3${\times}$. If the time-based decoder outputs an incorrect value, it could output
110 when the input data is +3, and 100 when it is -3. To overcome the clock-q delay
nonlinearity, an error correction block is proposed. The error correction block is
a circuit that corrects the incorrect time-based decoder output signal. A 110 output
indicates that the input data is +3, and a 100 output indicates that the input data
is -3. By correcting the error to match the corresponding data, the clock-q delay
nonlinearity of the sampler can be overcome. Fig. 8 shows the error correction block. It outputs 111 when the TB signal is 110, and outputs
000 when the TB signal is 100. To summarize, the time-based decoder can overcome the
comparison when the input voltage difference is 2${\times}$ and 3${\times}$. Therefore,
the timing margin of the difference of sampler delay has been increased and the sensitivity
of the time-based decoder has been improved.
Fig. 8. Block diagram of error correction block.
Table 1. Time-based decoder output according to input voltage difference
|
Input PAM-4 Signal
|
+3
|
+1
|
–1
|
–3
|
Reference voltage
|
Input voltage difference
|
REF3/REF2
|
0× / 1×
|
1× / 0×
|
2× / 1×
|
3× / 2×
|
REF2/REF1
|
1× / 2×
|
0× / 1×
|
1× / 0×
|
2× / 1×
|
REF1/REF0
|
2× / 3×
|
1× / 2×
|
0× / 1×
|
1× / 0×
|
Output of
time-based decoder
|
Thermometer Code
|
TB32
|
1
|
0
|
0
|
0(1)
|
TB21
|
1
|
1
|
0
|
0
|
TB10
|
1(0)
|
1
|
1
|
0
|
3. Phase Detecting Method (Error Sampler)
The proposed PD utilizes pattern-based PD. Pattern-based PD is a PD that performs
phase detection based on consecutive data patterns. The proposed PD determines the
early/late of the clock based on three consecutive data.
Fig. 9 shows the operation principle of the proposed PD. The current data determines which
reference voltage to use. And the PD determines the early/late of the clock phase
according to the current error(e[n]) based on reference voltage. For example, if the
current data(d[n]) is +3, the phase information is extracted using the sign of e$_{3}$[n]
relative to REF3. For a monotonically increasing pattern, if the clock is early, e[n]
outputs ‘-1’ because e[n] is low compared to the reference voltage. And if it is late,
e[n] outputs ‘+1’ because e[n] is higher. Conversely, if the clock is early, e[n]
outputs ‘+1’, and if it is late, e[n] outputs ‘-1’.
Fig. 9. Operation principle of proposed phase detector.
All the data patterns used in proposed PD is listed in Fig. 10 and Table 2. Only monotone increasing or monotone decreasing data patterns are employed. The
reason for choosing the data patterns is as follows: The dominant first pre- (h$_{-1}$)
and post-cursor (h$_{+1}$) ISI are considered. If both cursors are the same size (h$_{-1}$=h$_{+1}$),
the data patterns whose sum of the pre-cursors and post-cursors in d[n] is either
0 or ${\pm2h}_{-1}$(or ${\pm2h}_{+1}$) are used. Because data patterns less affected
by ISI are used, CDR lock point fluctuation is minimized. The proposed PD uses 24
data patterns, and the transition density is 0.375 (=24/4$^{3}$).
Fig. 10. Data patterns used in proposed PD: (a) Pure monotone; (b) Monotone and stay; (c) Stay and monotone.
Fig. 11 is the timing diagram of the proposed PD. First, PD identifies the data pattern based
on three consecutive data. And it determines whether it is the pattern used by the
proposed PD and whether it is a rising or falling pattern. If the data pattern belongs
to one of the 24 cases, it determines the early/late based on the rising/falling information
and error. Since the data pattern judgment is completed based on d[n+1], early/late
is determined using retimed e[n].
Fig. 11. Timing diagram of proposed phase detector.
Table 2. Data patterns used in proposed PD
d[n–1]
|
d[n]
|
d[n+1]
|
e[n]
|
PD
|
+3
|
+3
|
–3
|
e3[n] = –/+
|
L/E
|
+3
|
–1
|
L/E
|
–1
|
+3
|
E/L
|
–3
|
+3
|
E/L
|
+3
|
+1
|
–1
|
e2[n] = –/+
|
L/E
|
+3
|
–3
|
L/E
|
+1
|
–1
|
L/E
|
+1
|
–3
|
L/E
|
–1
|
+3
|
E/L
|
–1
|
+1
|
E/L
|
–3
|
+3
|
E/L
|
–3
|
+1
|
E/L
|
+3
|
-1
|
–1
|
e1[n] = –/+
|
L/E
|
+3
|
–3
|
L/E
|
+1
|
–1
|
L/E
|
+1
|
–3
|
L/E
|
–1
|
+3
|
E/L
|
–1
|
+1
|
E/L
|
–3
|
+3
|
E/L
|
–3
|
+1
|
E/L
|
+3
|
-3
|
–3
|
e0[n] = –/+
|
L/E
|
+1
|
–3
|
L/E
|
–3
|
+3
|
E/L
|
–3
|
+1
|
E/L
|
All other cases
|
STAY
|
V. SIMULATION RESULTS
1. Simulation of Consecutive Bit Responses
To verify the receiver with proposed CDR, the entire block was designed and simulated
in 65 nm CMOS process. All simulations have been done with post-layout. In addition,
an FR4 type 210 mm channel was used.
Fig. 12 shows the simulation setup to check three consecutive bit responses of the PAM-4
signal after passing through the channel and CTLE. Fig. 13 is the simulated three consecutive bit responses of all cases that three consecutive
PAM-4 signals can produce. The blue lines are the data patterns used by the proposed
PD, and the black lines are the data patterns not used. And the red line indicates
the level of the reference voltage. Simulations show that unused data patterns either
do not pass through the reference voltage level or meet far from the ideal sampling
phase. This can cause the CDR lock point to fluctuate and increase the clock jitter.
On the other hand, the data patterns used by the proposed PD meet the reference voltage
level in a narrow range, which reduces the fluctuation of the lock point while ensuring
transition density. Fig. 14 is an eye diagram of the measured CDR. It has a peak-to-peak jitter of 9.35 ps, which
is the proof that lock point is less fluctuated.
Fig. 12. The simulated SBR of channel with CTLE and test setup for three consecutive bit responses.
Fig. 13. Simulation of three consecutive bit responses.
Fig. 14. Eye diagram of (a) equalized data; (b) recovered clock (3.125 GHz) for 10,000 UI samples.
2. Simulation of Jitter Tolerance
To verify the transition density and loop BW, a simulation of jitter tolerance is
performed. Fig. 15 shows the test setup for jitter tolerance simulation. To increase the reliability
of the verification, a noise environment was considered. The noises considered are
as follows: ① TX clock jitter (RJ+SJ) ② Reference voltage noise ③ VCO phase noise.
To simulate jitter tolerance, a sinusoidal jitter source is used to generate the input
signal at the TX clock. The maximum jitter amplitude that can be tolerated per frequency
is simulated by increasing the jitter amplitude until reaching the threshold BER at
each jitter frequency.
Fig. 15. Test bench for jitter tolerance simulation.
To verify the improved jitter tolerance, proposed CDR and conventional PAM-4 baud-rate
CDR which employs SS-MMPD are compared. All blocks except the PD and Decoder block
were designed the same to enable jitter tolerance comparison based solely on phase
detecting performance. Fig. 16 shows the jitter tolerance comparison. Proposed CDR has most improved jitter tolerance
in all the jitter frequency and has wide loop BW. The conventional CDR using SS-MMPD
has a transition density of 0.125, while the proposed CDR has a transition density
of 0.375. Therefore, the proposed CDR has a wider loop bandwidth and better jitter
tolerance.
Fig. 16. Simulation result of jitter tolerance.
3. Power Consumption
The proposed 25-Gbps PAM-4 receiver consumes 19.6~mW of power at a supply voltage
of 1.2 V. Fig. 17 shows the power breakdown of the proposed PAM-4 receiver. And Table 3. shows the performance comparison between this paper and other PAM-4 receivers using
baud-rate CDR. The proposed CDR has a high transition density and low power consumption
compared to other receivers.
Fig. 17. Power breakdown of proposed receiver.
Table 3. Performance summary and comparison with previous works
|
This Work
(Post-layout Sim.)
|
[5]
(Measurement)
|
[7]
(Measurement)
|
[8]
(Measurement)
|
Technology
|
65 nm
CMOS
|
40 nm
CMOS
|
40 nm
CMOS
|
28 nm
CMOS
|
Modulation
|
PAM-4
|
PAM-4
|
PAM-4
|
PAM-4
|
Data Rate [Gb/s]
|
25
|
48
|
64
|
52
|
Channel Loss [dB]
|
7.1
|
4
|
6
|
7.1
|
Clock Architecture
|
Quarter-rate
PLL-based
|
Half-rate
PI-based
|
Quarter-rate
PLL-based
|
Quarter-rate
PLL-based
|
PD type
|
Baud-rate
(Pattern-based)
|
Baud-rate
(Stochastic PD)
|
Baud-rate
(Transition-Weighted)
|
Baud-rate
(Pattern-based)
|
Equalization
|
CTLE
|
CTLE
1-tap DFE
|
CTLE
2-tap DFE
|
CTLE
|
# of COMPs per UI
|
4
|
5
|
4
|
4
|
Transition Density
|
0.375
|
0.111
|
0.1875
|
0.125
|
Power[mW]
|
19.6
|
116.3
|
152
|
43.1
|
Energy Efficiency [pJ/bit]
|
0.784
|
2.42
|
2.37
|
0.83
|
VI. CONCLUSIONS
This paper proposes a 25-Gbps PAM-4 baud-rate CDR with high jitter tolerance. A shared
sampler method is that one sampler is act as data sampler and error sampler simultaneously.
By using four samplers per UI, an energy efficient design is presented by reducing
the burden of the clock buffer and AFE. In addition, since all samplers are used for
phase detection, more transitions are detected than conventional SS-MMPD. With a high
transition density of 0.375, proposed CDR has a high jitter tolerance. In addition,
since the clock phase error is determined based on three consecutive data, the effect
of ISI is reduced, and the CDR lock point fluctuation is minimized.
ACKNOWLEDGMENTS
This work was supported by Inha University. CAD tools and chip fabrication were
provided by IDEC.
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Seoung-Geun Cho was received the B.S. degree in Electronic Engi-neering from Inha
University, Incheon, South Korea, in 2023. He is currently pursuing the M.S degree
in Electrical and Computer Engineering with Inha University. His research interests
include PLL/CDR, Equalizer, highspeed serial interface, and transceiver design for
PAM signaling.
Jin-Ku Kang received the Ph.D. in electrical and computer engineering from North
Carolina State University, Raleigh, NC, USA, in 1996. From 1983 to 1988, he was with
Samsung Electronics, Inc., Korea, where he was involved in memory design. In 1988,
he was with Texas Instrument in Korea. From 1996 to 1997, he was with Intel Corp.,
Portland, OR, USA as a senior design engineer, where he was involved in high-speed
I/O and timing circuits for processors. Since 1997, he has been with Inha University,
Department of Electronics Engineering, in Incheon, Korea. His research interests include
high-speed/low-power mixed-mode circuit design and prototyping with FPGA for high-speed
serial interfaces.