ParkDong Wuk1,2
ByeonKi Ryun1
LeeGi Sung1
LimTae Hee3
JoKyoung Hwan3
OhTae Hyoun1
ParkHyung Chul4
EoYun Seong1,2
-
(Department of Electronic Engineering at Kwangwoon University, Seoul, 139-701, Korea)
-
(Silicon R&D Corp. Seongnam-si, Gyeonggi-do, 13510, Korea)
-
(LIG Nex1 Company, Seongnam-si, Gyeonggi-do, 13510, Korea)
-
(Department of Electronic and IT Media Engineering at Seoul National University of
Science and Technology, Seoul, 01811, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
NB-IoT, RF transceiver, Korean M-Bus, high power transmitter, low sensitivity
I. INTRODUCTION
Nowadays, a variety of low-rate RF communication standards has been developed for
the IoT application and wireless sensor networks [1]. As a particular example, the wireless M-Bus (Metering-BUS) standard specified in
EN 13757-4:2013 is one of the wireless communication technologies developed for the
reading of electricity, gas-, water-, heat-meters. The collection and analysis of
power information in the smart grid is essential. The collected power information
can be used to efficiently utilize the power such as power generation and distribution.
Moreover, the convenient and efficient electricity charging system without the manual
reading of utility meters can be realized in the aid of smart metering service. Recently,
many countries around the world have been establishing the international standards
or unique standards for the smart meter communication. In South Korea, Korean M-Bus
standard (SPS-KTC C 1018-2-7360) is also developed as a domestic regulation for the
remote metering service. The frequency band of Korean M-Bus is allocated in the range
of 262-264 MHz rather than 400 or 900 MHz, so that the RF transceiver should be developed
for the newly allocated band. The key requirement of the smart metering includes the
battery-powered operation, the long-distance secure and reliable communication quality
in the urban environment, and low-cost device. These issues depend upon the operating
frequency, power consumption, range, and other security issues.
In this paper, we present the first fully integrated CMOS RF transceiver for the metering
devices compatible with Korean M-Bus standard. In the range of 262–264 MHz, the allocated
channel bandwidths and spacing are 12.5/50/200/400 kHz and 12.5/37.5/300 kHz respectively.
The 12.5 kHz is very narrow band so that the receiver is vulnerable to the DC noise
or 1/f noise caused by the circuits and transistors if the direct conversion receiver
is used. To overcome these problems, the low IF Rx (Receiver) architecture is adopted
and the DC noise including 1/f noise is suppressed sufficiently by the analog BPF
(Band-Pass Filter). The filtering of the side channels would be performed in the digital
BPF as well as the baseband analog BPF. The designed M-Bus RF transceiver should support
all of the FSK/GFSK/4GFSK modulations as indicated in the standard. This article is
organized as follows. In Section II, the RF transceiver architecture and the circuit
block designs are described. In Section III, the measurement results are presented,
and the conclusion is finally given in Section IV.
II. ARCHITECTURE AND CIRCUIT DESIGN
1. 262 MHz RF Transceiver Architecture
Fig. 1 shows the full architecture of the designed 262 MHz RF transceiver, which includes
the direct up-conversion transmitter, low IF receiver and synthesizer block. The transmitter
adopts the direct up-conversion architecture and the baseband I/Q symbol signals are
transmitted to a digital-to-analog converter (DACs) followed by a 4th order active
LC low-pass filters. Since FSK/GFSK/4FSK modulation is a constant envelop modulation,
a nonlinear drive amplifier with high efficiency can be used. The needs of the simple
RF architecture, low power consumption, and removal of 1/f noise lead us to employ
the low IF architecture as the suitable candidate for our narrow band M-BUS transceiver.
Considering the very narrow channel bandwidth less than the several hundreds kHz,
the 1/f noise and DC noise may overwhelm our desired signal band and degrades the
SNR (Signal to Noise Ratio) seriously if the direct conversion receiver is employed.
Since the channel bandwidths for 262 MHz Korean M-BUS are 12.5/50/200/400 kHz, the
IF frequency of the receiver is determined to be 400 kHz, which corresponds to the
widest channel. Hence the sampling clock rate of ADC (Analog to Digital Converter)
is 2.4 MHz, which is the 4 times the maximum analog frequency of 600 kHz for the double
oversampling. The FSK/GFSK/4FSK modulations suggested in the standard need only SNR
around 12 dB, so that 4 or 6 bits ADC is sufficient only for the reception of the
main signal.
Fig. 1. Block diagram of narrow band M-BUS TRx IC.
The sensitivity of the receiver is determined by the noise power at room temperature
corresponding to -174 dBm/Hz, NF, BW and the required SNR [3]. According to the standards, the required SNR for FSK/GFSK/4FSK modulation with a
PER of 10$^{-1}$ is within 12 dB, and the maximum required bandwidth is 200 kHz. If
the overall NF of the receiver is maintained below 4 dB, the target sensitivity can
be calculated to be below -105 dBm.
Although the requirement for Adjacent Channel Interference (ACI) is not officially
defined, interference higher than desired signals from adjacent channels can degrade
the SNR of the desired signal. We have set our target specification as more than 40
dBc suppression of ACI within the 262-264 MHz in-band range. To mitigate the ACI,
the poly-phase BPF is employed in the BBA (base band analog) block in the transceiver,
The poly phase BPF in the BBA stage is implemented as 4th order Butterworth filter,
which performs ACI rejection to out of bandwidth poly phase BPF about several kHz.
However, for adjacent channels corresponding to a minimum channel spacing of 12.5
kHz, it is challenging to implement analog filtering in the analog block. So, rejection
for the minimum channel spacing will be handled in the DSP part. Both the desired
signal and interference signals are transmitted to the DSP part together. Subsequently,
interference signals will be removed using a Digital Front-End (DFE) through a Finite
Impulse Response (FIR) filter. Therefore, in the analog block, the desired signal
is transmitted to the Digital Signal Processor (DSP) part, including interference
signals with amplitudes at least 40 dBc greater than desired signal without degrading
linearity and SNR. Since the SNR required by the modulation method specified in the
standard is 40 dB greater than the required SNR, the resolution of ADC is determined
to be 10 bits with some margin [2].
Considering the LO frequency synthesizer, the fractional-N PLL and the 1/2 frequency
divider is used for IQ LO generation for the 12.5 kHz spaced channels.
2. Receiver RF Front End Design
The calculated target NF (Noise Figure) of full receiver chain is below 4 dB for the
high sensitivity with the required SNR of 12 dB, which is not stringent to the receiver
design even if considering the additive NF due to the external passive loss. The RF
front-end of the receiver consists of a S2D (Single to Differential) LNA, a RF VGA
(Variable Gain Amplifier), and a passive mixer with the TIA (Trans-Impedance Amplifier).
A noise cancelling common-gate common-source (CGCS) amplifier is used as the S2D LNA
to obtain the low noise figure and the single to differential signal conversion, as
shown in Fig. 2. Since CS and CG paths have the amplitude and phase mismatch, the capacitive cross
coupled structure is also adopted to reduce the mismatch and improve the noise figure.
Fig. 3 shows the circuit schematics of the RF VGA. The RF VGA is a cascode amplifier with
the shunt CMOS transistor switch (M$_{5}$ and M$_{6}$) at the differential drain nodes
of common source transistors to control the gain and enhance the linearity of the
receiver. The mixer employs the passive mixer topology with the TIA to also control
the gain and linearity. In the passive mixer, since the gate bias and the size of
the LO switch transistors dominate NF and IP3 characteristics, the bias and the size
for the LO switch are optimized independently. The LO buffer amplifier, which drives
the LO ports of mixer, is designed as a resistive feedback inverter type amplifier.
The inverter type LO buffer can make a sufficient LO swing with the small current
consumption and small LO signal distortion. The simulated gain of the RF front end
from LNA to mixer ranges from 49 dB to 28 dB, and NF is 2.7 dB, respectively. The
IIP3 of the RF front end is -32 dBm at the maximum gain.
Fig. 2. Noise cancelling common-gate common-source LNA.
Fig. 3. Circuit schematic of RF VGA.
3. Receiver BBA (Base Band Analog) Design
The BBA (Base Band Analog) block includes a PPF (Poly-Phase Filter), shown in figure.
4, a 3-stage PGA (Programmable Gain Amplifier), and a buffer amplifier. Because the
gain of the RF front-end is so large and the side channel rejection is more important,
the PPF stage precedes the PGA stage. The PPF is a 4th order Butterworth poly-phase
BPF (Band Pass Filter), whose IF or center frequency is 400 kHz and the bandwidth
is also 400 kHz for the low IF receiver. The 4th order PPF is composed of two 2nd
order biquad BPFs whose design methodology had been reported in detail in some literatures
[2,3]. And each double pole biquad is realized with the active RC filter using the op-amp.
The bandwidth of the pass band is slightly tunable. The simulated IRR (Image Rejection
Ratio) is 48.7 dBc. Since the target requirement of the ACI (Adjacent Channel Interference)
suppression is decided to be 40 dBc, the 4th order filter is useful and the additional
rejection is performed in the digital filter in the DFE (Digital Front- End) block.
The following block is a 3-stage PGA. The PGA block consists of the op-amp based inverting
amplifier, whose gain is variable using the switched feedback resistors. The two stages
are the coarse gain stages with the gain step of 5 dB. And the final stage is a fine
gain stage with the 1 dB step. The gain of the PGA stage changes linearly by the digital
control. The overall BBA gain ranges from 65.3 dB down to 0.5 dB with the 1 dB resolution.
The NF of the BBA block is 36.7 dB at the maximum gain. To cancel the DC offset voltages,
the DCOC (DC Offset Cancellation) loop is added in each amplifier stage to prevent
the saturation and DC noise voltage. The BBA performances and stability are simulated
and checked in the various conditions of the process, voltage, and temperature variations.
The ADC (Analog to Digital Converter) is a SAR (Successive Approximation Register)
type 12-bit ADC for the SNR margin to discriminate between the small desired signal
and the strong near-channel interference. The ADC adopts the monotonic switching capacitive
DAC and the input capacitance is 72.9 pF. The simulated SNR and SFDR are more than
64 dB and 66.7 dB at the 2.5 MHz sampling rate, respectively.
4. Transmitter RF and BBA Design
The transmitter is a direct-conversion I/Q modulator. The 8-bit current–steering digital-to-analog
converter (DAC) drives the BBA stage. The DAC has two segmentations of the thermometer
coded 4-bit MSB and the binary weighted 4-bit LSB parts. The differential current
output is from 1 ${\mu}$A to 255 ${\mu}$A. The DAC output current with the unwanted
spurious signal is filtered by the LPF (Low Pass Filter) in the Tx BBA stage in order
to satisfy the Tx output spectrum mask requirement. The LPF is the 2nd order Butterworth
LPF using the active RC topology and it is enough to remove the unwanted spurious.
For the Tx BBA gain control, a 4-bit controlled PGA stage is added in front of the
up-conversion mixer. The gain control range of PGA is 16 dB and the gain step is 1
dB. In designing the up-conversion mixer, the resistive degeneration is used for the
linearization of base band input stage and a linear current mirror amplifier is following
without transconductor nonlinearity degradation. As the load of mixer output, an active
load is used to maximize the gain without the LC tank. A D2S (Differential to Single-ended)
amplifier is following the mixer to convert the RF signal in the single ended form.
Fig. 5 illustrates the operations of the D2S amplifier and the driver amplifier. As shown
in Fig. 5(a), the D2S amplifier utilizes the combined push-pull operation of the paired NMOS and
PMOS transistors. The final drive amplifier is a common source cascode amplifier with
the external RF inductor and capacitor load as shown in Fig. 5(b). The cascode configuration is used for better isolation between input and output
stage. And since the target transmitted power is more than +15 dBm, the thick oxide
NMOS is employed as the common gate transistor for the prevention of the breakdown
due to the high output voltage swing. And in order to enhance the power efficiency
of the driver amplifier, the bias point is set in the near class B, which is not problematic
in the constant envelope modulation such as N-FSK and GFSK. The gain of driver amplifier
is controlled digitally by switching the transconductance of the parallel array of
common source transistors M$_{\mathrm{1\backslash \_ 1}}$ and M$_{\mathrm{1\backslash
\_ 2}}$.
Fig. 4. (a) Block diagram of 4th order Poly-Phase Filter; (b) Transfer function.
Fig. 5. Circuit schematic of (a) D2S amplifier; (b) drive amplifier.
5. Fractional-N PLL Design
A fractional-N frequency synthesizer is designed as shown in Fig. 6. The IQ LO (Local Oscillation) signal is generated through the various CML (Current
Mode Logic) dividers and the frequency can be selected in the sub-GHz range. In this
work, 262 – 264 MHz LO signal is used and generated through the 8-divider. A CMOS
cross-coupled pair LC VCO is used for the symmetric output with a differential on-chip
inductor in the tank circuit. In order to tune the oscillation frequency, the 6-bit
capacitor array is switched digitally. The oscillation frequency of the integrated
VCO ranges 1.6 to 2.4 GHz. The 16-bit sigma-delta modulator is adopted for the fractional-N
PLL and provides the 585.9 Hz frequency resolution. The loop filter is the 3rd order
low pass filter to obtain a sufficient phase margin and mitigate the switching noise
caused by the charge pump. All of R and C components of the loop filter are integrated
and the capacitor can be trimmed. The simulated loop bandwidth is about 200 kHz and
the lock time for the channel settling is around 35 ${\mu}$s. The simulation gives
the phase noise of -126 dBc/Hz@1MHz offset. The total current consumption of the designed
PLL is 12.2 mA including LO buffer amplifier.
Fig. 6. Block diagram of fractional-N frequency synthesizer.
III. MEASUREMENT RESULTS
The fully integrated 262 MHz RF transceiver for the Korean M-Bus is fabricated in
the 0.18-${\mu}$m CMOS process. Fig. 7 shows the IC micro-photograph and the photo of the test board. The IC die area is
3.3 ${\times}$ 3.1 mm$^{2}$. The 1.8-V voltage supply is used and the current consumption
is 23 mA in receive mode and 21 mA in transmit mode at 0 dBm, respectively. However,
at the high power mode of +15 dBm, the transmit mode consumes the additional 26 mA
current form the external 3.3 V source.
Fig. 7. Photos of 262 MHz RF Transceiver IC and test module.
Fig. 8 shows the measured results of LO phase noise at 262 MHz and -124.93 dBc@1MHz offset
agrees well with the simulated results. The LO frequency can be generated with the
high frequency resolution for all the channels proposed in the Korean M-Bus standard.
Fig. 8. Measured phase noise of 262 MHz LO signal.
The transmitted power and OIP3 characteristics vs. BBA input power are shown in Fig. 9, which shows the fundamental tone, the 3rd tone, and OIP3. The saturated power of
the transmitter is more than 15.4 dBm and OIP3 is about 24 dBm. The transmitter gain
control range is 27 dB with 1 dB gain step by controlling the driver amplifier and
Tx BBA stage. The receiver gain ranges from 113.5 dB at maximum down to 17.5 dB at
minimum by controlling the RF and BBA gain controls, while the gain step of BBA stage
is 1 dB. After some input matching, NF of the receiver at the maximum gain is measured
as 3.85 dB, which is slightly below the target of 4 dB. The measured IIP3 of the receiver
is -28 dBm at the maximum gain and it is enhanced at the LNA low gain mode.
Fig. 9. Measured transmitter power and OIP3 characteristics.
With the help of the FPGA based modem part, the modulated transmitted spectrum and
the sensitivity can be measured with the equivalent air path loss replaced by the
tunable attenuator and cables. Fig. 10 presents the modulated spectrums of GFSK signals at the transmitter output for 12.5
kHz (upper) and 200 kHz (lower) bandwidths, respectively. After connecting the transmitter
to the receiver through the tunable attenuator and cables, the equivalent path loss
is applied and the sensitivity can be estimated by measuring the RF power at the receiver
input when the calculated BER or PER in the modem part meets the required error rate.
Fig. 11 shows the sensitivity measurement environment and the measured PER curve with 600
kHz offset ACI vs. receiver input power. The measured sensitivity of 200 kHz GFSK
signal is lower than -110.4 dBm where PER (Packet Error Rate) is 0.8 or BER (Bit Error
Rate) is 10$^{-2}$, which is specified in the standard EN 13757-4:2013. And if we
redefine the target PER as 10$^{-1}$ for the comparison with the other studies, the
sensitivity is -105.4 dBm at 200 kHz BW. If we assume that the receiver input signal
is -105.4 dBm the Rx gain is programmed to be about 95 dB, the amplified signal becomes
-10.4 dBm and the noise power with 200 kHz BW is -22.1 dBm at the ADC input, respectively.
Then, the calculated SNR is 11.7 dB, which agrees well with the theoretically calculated
BER or PER requirement of GFSK modulation. Table 1 summarizes and compares the measured performances of sub-GHz RF transceiver with
the other studies [4-11].
Fig. 10. Measured Tx spectrums for mode C & N (GFSK).
Fig. 11. Sensitivity measurement set-up and measured PER curve with 600 kHz offset ACI.
Table 1. Comparison of sub-GHz RF transceivers
|
Ref.
|
Band
|
PLL PN
|
Rx NF
|
Rx Sensitivity
|
Rx ACR
|
Tx power
(max)
|
DC power (Tx/Rx)
|
CMOS
Tech.
|
|
[4]
|
922 MHz
|
-110dBc
@10kHz
|
-
|
-94 dBm
@BER <10-4, 500kbps
|
36 dBc
@1 MHz offset
|
+2 dBm
|
3.3/4.6 mW
|
65 nm
|
|
[5]
|
750-930 MHz
|
-120.7dBc
@1MHz
|
4 dB
|
-92 dBm @ 1MHz
SNR=17.8 dB
|
-
|
13.6 dBm
|
18.9/95.8 mW
|
180 nm
|
|
[6]
|
169/300/400
/900 MHz
|
-128 dBc
@2 MHz
|
6 dB
|
-101.5 dBm
@ 100kbps, BER<10-3
|
-
|
+10 dBm
|
9.8/27.6 mW
|
65 nm
|
|
[7]
|
750-930 MHz
|
-
|
4.01 dB
|
-107 dBm@120 kHz
SNR=10.5 dB
|
-
|
+23.2 dBm
|
25 mW
|
180 nm
|
|
[8]
|
310/450/900
MHz
|
-
|
5.5 dB
|
-
|
60 dBc
@ 400 kHz offset
|
+18 dBm
|
59.4/126 mW
|
140 nm
|
|
[9]
|
900 MHz
|
-108dBc @1MHz
|
9 dB
|
-98 dBm @BPSK
|
48 dBc
@ 5 MHz offset
|
0 dBm
|
25.2/28.8 mW
|
180 nm
|
|
[10]
|
450-960/1561-2220 MHz
|
-
|
-
|
-112.5(LB) /
-111.9(HB) dBm @N/A
|
-
|
+22.2 dBm
|
585/53 mW
|
40 nm
|
|
[11]
|
450-960/1561-2220 MHz
|
-
|
-
|
-125 dBm @N/A
|
-
|
+23 dBm
|
1610/50 mW
|
28 nm
|
|
This work
|
262 MHz
|
-124.9 @1MHz
|
3.85 dB
|
-110.4/-105.4 dBm
@200 kHz, PER <0.8/10-1
|
56 dBc
@ 600 kHz offset
|
+15.4 dBm
|
41.4/37.8 mW
|
180 nm
|
IV. CONCLUSIONS
A fully integrated 262 MHz CMOS RF transceiver for the wireless M-Bus (Metering-BUS)
standard is presented. The chip is implemented in 0.18 ${\mu}$m RF CMOS process and
the die area is 3.3 mm ${\times}$ 3.1 mm. It consumes 41.4/37.8 mW in transmit/receive
mode respectively. The receiver adopts the low IF architecture with 4th order poly-phase
filter for ACI/AACI rejection in BBA stage. The driver amplifier is designed in the
same fashion with the power amplifier design to achieve high efficiency and high output
RF power. The measured Tx output power/OIP3 are +15.4/+24 dBm respectively and the
receiver sensitivity is -105.4 dBm for PER 10$^{-1}$ and 50-kbps GFSK modulation with
56 dBc ACR. This work is the first CMOS RF transceiver for the 262 MHz dedicated wireless
metering services specified in Korean M-Bus standard.
ACKNOWLEDGMENTS
This research was supported by Research Program through the National Research
Foundation of Korea (NRF) funded by the Ministry of Science and ICT (No. NRF-2021M1B3A3102380)
and also by LIGNEX1 PGM2 group.
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Dong Wuk Park received B.S. and M.S. degrees in Electronic Engi-neering from Kwangwoon
University, Seoul, Korea, in 2015 and 2017, respectively. From 2017 to 2019, he was
RF engineer with Point2 technology inc., Seoul, Korea. Since 2019, he joined Silicon
R&D inc. and he is working toward the Ph.D degree from Kwangwoon University, Seoul,
Korea, developed CMOS RF/analog transceiver integrated circuits and systems. His current
interests include RF/analog ICs for wireless communication and UWB.
Ki Ryun Byeon received the B.S., M.S. degrees in Electronic Engi-neering from Kwangwoon
University, Seoul, Korea, in 2021 and 2023, respectively. In 2023, he joined ABOV
Semiconductor Co. Ltd, developed CMOS RF/analog integrated circuit. His current interests
include CMOS-based PLL for wireless communications.
Gi Sung Lee received the B.S. degree in Electronic Engineering from Kwangwoon University,
Seoul, Korea, in 2023. Since 2023, he has working toward his M.S. degree at the same
university. His current research interests include CMOS RF/analog IC design for wireless
communication systems.
Tae Hee Im is a chief engineer at LIG Nex1 in the field of weapon data links mounted
on guided missile. He is developing data link equipment based on rf transceiver SoC
and is trying to apply it to the field of guided missiles.
Kyoung Hwan Jo currently serves as the team leader of the PGM Core Technology Research
Institute at LIG Nex1 in South Korea. His current research focuses on the application
and utilization of RF transceiver SoC for data links, UWB transceiver chips for proximity
fuze, and FMCW transceiver chips for radio altimeters embedded in guided weapons.
Tae Hyoun Oh received B.S., and M.S., degrees in Electrical Engi-neering from Seoul
National University in 2005 and 2007, respectively. He received his Ph.D. degree in
Electrical Engineering from the University of Minnesota, Minneapolis under the supervision
of Dr. Ramesh Harjani. His doctoral research is focused on high-speed I/O circuits
and architectures. During the summer of 2010, he worked on I/O channel modeling at
AMD Boston Design Center, MA. In the fall semester of 2011, he researched on I/O architecture
and jitter budgeting of the link at Intel Corp., CA. From fall of 2012, he joined
the IBM system technology group, NY. and worked on performance verification of high-speed
decision feedback equalizer for server processors. Since spring of 2013, he joined
at the department of electronic engineering in Kwangwoon university in Seoul, Korea
as an assistant professor. His current research interest is focused on clock generation
IC design.
Hyung Chul Park received the B.S., M.S., and Ph.D. degrees in electrical engineering
from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea,
in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was a SoC Design Engineer
with Hynix Semiconductor, Seoul, Korea. From 2005 to 2010, he was an Assistant Professor
at the Hanbat National University, Daejeon, Korea. In 2010, he joined the faculty
of the Department of Electronic and IT Media Engineering, Seoul National University
of Science and Technology, Seoul, where he is currently an Associate Professor. His
current research interests include wireless modulation/demodulation algorithms, system
design/ implementation, and interface study between RF/IF stages and digital signal
processing.
Yun Seong Eo received the B.S., M.S., and Ph. D degrees in Electrical Engineering
all from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea,
in 1993, 1995 and 2001, respectively. From 2000 to 2002, he had been with LG Electronics
Institute of Technology, Seoul, Korea, where he was involved in designing RF integrated
circuit (RFICs) such as VCO, LNA, and PA using InGaP HBT devices. In September 2002,
he joined Samsung Advanced Institute of Technology, Yongin, Korea, where he developed
5-GHz CMOS PA and RF transceivers for 802.11n target, and was also involved in the
development of 900 MHz RF identification (RFID) and 2.4-GHz ZigBee RF transceivers.
In September 2005, he joined Kwangwoon University, Seoul, Korea, where he is currently
a professor with Electronics Engineering department. Recently, he has developed so
many RF transceiver ICs for the WPAN/WBAN and narrow band IoT devices. And he has
been focusing on CMOS UWB and FMCW Radar ICs for surveillance system and proximity
fusing. In 2009, he founded Silicon R&D Inc, where he is CEO and develops CMOS based
UWB radar ICs and low power/rate communication RFICs.