I. INTRODUCTION

Scaling down, which involves reducing the size of semiconductor devices, is a key driving force in the modern semiconductor industry ^[1-4]. Continuous research activities for scaling down have been conducted in the past and present to enhance the performance and integration density of devices. However, as the size of semiconductor devices decreases, the influence of parasitic resistance and parasitic capacitance increases. Fig. 1 illustrates the positions where parasitic resistance and parasitic capacitance can occur in semiconductor device structures. Firstly, Fig. 1(a) depicts the structure of a component where parasitic capacitance can occur. When the gate electrode is formed in a way that it covers the S/D electrode, unintended parasitic capacitance is generated due to the insulating layer and electrodes. Additionally, parasitic capacitance represents the capacitance that accumulates charge within semiconductor devices. As the size decreases, the distance between devices decreases and the junction area increases, leading to an increase in parasitic capacitance. This can slow down the device's operation, cause interference between signals, and result in energy loss. Fig. 1(b) illustrates the structure of a component where parasitic resistance can occur. When there is a distance between the gate electrode and the S/D electrode, a resistance element arises that is not directly influenced by the voltage applied to the S/D but remains unmodulated by the gate voltage. Parasitic resistance refers to the resistance generated within semiconductor devices when current flows. As the size decreases, the cross-sectional area of the current path decreases, leading to an increase in parasitic resistance. This restricts the flow of current and can result in increased power consumption. Therefore, the increase in parasitic resistance due to scaling down can have a negative impact on the device's operating speed and power efficiency.

Fig. 1. Two types of structures and the degradation factors for each are illustrated: (a) when the gate overlaps with the S/D electrode, indicating the location of parasitic capacitance; (b) when the gate is underlapping with the S/D, indicating the occurrence of parasitic resistance in this case.

To address these issues, self-aligned structures play a crucial role. Self-aligned structures are a technique used in the semiconductor manufacturing process to align various components of the device ^[5-7]. This allows for the minimization of parasitic resistance and parasitic capacitance while maintaining a small device size. The self-aligned structure minimizes parasitic capacitance by reducing junction area and optimizes current paths to minimize parasitic resistance. This improves the operating speed and reduces power consumption of semiconductor devices. Additionally, self-aligned structures reduce interference between devices and enhance signal accuracy and reliability. One prominent process method for self-aligned structures used in research activities is the T-gate structure. The T-gate structure shapes the cross-section of the gate in a T-like manner to ensure that the top width is wider than the bottom, effectively minimizing parasitic resistance. However, this approach involves the inconvenience of depositing the gate electrode in two steps, leading to additional processing costs. Therefore, in this study, a new process method is proposed to achieve more efficient formation of self-aligned structures. By depositing the gate structure stack at once and using a lift-off technique, it is possible to simultaneously form the spacer that controls short circuits between the gate electrode and other electrodes. This approach simplifies the process and reduces costs in research activities. Furthermore, the proposed method was validated by directly fabricating short-channel devices and ensuring their performance characteristics.

II. EXPERIMENTAL DETAILS

Fig. 2 illustrates the fabrication method of the self-aligned structure proposed in this study. To validate a more efficient approach, we utilized a transistor with a simple fabrication process using a 2-D material as the channel. Therefore, we fabricated unit devices using graphene. 2D channel have been researched for several years as alternatives to Si, and among them, graphene stands out for its easy availability and, most importantly, compatibility with Si processes. Additionally, the process of fabricating devices using graphene can be easily established. The primary goal of this study is to explore the feasibility of applying a novel self-aligned process and confirming its improved characteristics. Therefore, materials and processes essential for device fabrication were chosen based on their relatively high utility.

Fig. 2. A simplified and efficient method for fabricating self-aligned structures using gate stack (dielectric/electrode) simultaneous lift-off.

Initially, the material (graphene in this study) for the channel was transferred onto a SiO$_{2}$ substrate, followed by the deposition of electrodes for source/drain. Graphene was transferred using a wet-transfer method ^[8,9], where it was initially grown on Cu through thermal diffusion, and then patterned using photo lithography to the desired dimensions for the channel area. Subsequently, the source/drain electrodes were fabricated using a lift-off method with Cr/Au metals through photo lithography. To create short-channel devices, an E-beam lithography process was employed to achieve a 50 nm channel length. The method proposed in this study involves depositing a gate stack onto the lithographed pattern and implementing short-channel formation through lift-off. As the gate dielectric is also deposited on the sidewalls of the photoresist, spacers are simultaneously formed. Thus, the lithographed pattern size should be designed as channel length + spacer + spacer. After lithography, the gate dielectric and electrodes were sequentially deposited. In this study, Al$_{2}$O$_{3}$ (10 nm) and Au were deposited and formed through lift-off. Lastly, a thin metal electrode (Au) was deposited for the final implementation of the self-aligned structure.

III. RESULTS AND DISCUSSIONS

The self-aligned fabrication process proposed in this study focuses on verifying the successful retention of patterns when forming the gate stack using the lift-off technique. While increasing the thickness of the insulating layer can pose challenges, in the case of short channel structures, not only does the channel length decrease, but the gate dielectric thickness also decreases significantly, allowing for sufficient pattern retention and removal due to the thin thickness. The typical thickness of gate dielectric used in current semiconductor devices is approximately 10 nm. Therefore, in this research, Al$_{2}$O$_{3}$ with a thickness of 10 nm was chosen as the gate dielectric. After undergoing ebeam lithography, the deposition of gate dielectric and gate electrode stack (Al$_{2}$O$_{3}$ 10 nm / Au) was carried out, followed by lift-off, and efforts were made to confirm the proper formation of patterns using AFM and SEM.

As evident from the results in Fig. 3, it was confirmed through SEM that the patterning in the gate area was properly executed. Additionally, the uniformity of the gate stack was verified by examining the step height using AFM, confirming the proper formation of the gate electrode through a two-step validation process. The fabricated device was measured by sweeping the gate voltage from -3V to 3V while applying 1V and 2V to the drain electrode, in order to verify the self-aligned effect of the proposed spacer and self-aligned gate stack fabrication process. The characteristics of the device were measured and compared with and without the deposition of a thin metal electrode (Au) after lifting off the gate electrode. The 2-D channel used in this study is graphene, as mentioned earlier. Therefore, the on/off ratio is lower compared to Si devices, and changes in mobility characteristics occur around the Dirac point due to channel doping, but there are no difficulties in verifying the self-aligned structure, and it has advantages in easier fabrication and evaluation of the device. Additionally, since the structure of devices using different materials as the channel is fundamentally the same, the applied processes can be used without modification.

Fig. 3. Verification of the gate structure with the new self-aligned process: (a) Patterning verification using SEM; (b) Verification of gate stack formation (step height) using AFM.

Fig. 4(a) shows the results measured without the deposition of a thin metal (Au) for self-alignment. The Graphene FET undergoes changes in the curve based on the Dirac voltage. The Dirac voltage is typically situated at positive voltages and exhibits the minimum current at that point. Referring to this, the off current criteria were read near the Dirac voltage, and the on current criteria were set at -2V based on the characteristics of the FET fabricated in this experiment. Subsequently, the on/off ratio was determined based on these readings ^[10,11]. As seen in the graph, the on/off ratio is around 1.2-1.5, and the transconductance is around 0.1-0.2 mS. For the device with thin metal (Au) deposition for self-alignment, as shown in Fig. 4(b), the on/off ratio improved to around 2, and the transconductance increased more than two times to around 0.45 mS. While the on/off ratio remains lower compared to Si-based devices, it is crucial to acknowledge that this is inherent to the nature of graphene, which lacks a bandgap. However, with the application of the self-aligning structure, we can observe improvements in electrical characteristics, indicating a feasible enhancement in performance. Thus, even with the same channel length (50 nm), the electrical characteristics can vary by approximately two times depending on the presence or absence of self-alignment. By applying self-alignment, factors that degrade device performance can be minimized, and in this study, the source/drain electrodes were brought closer to the gate, serving the role of eliminating parasitic resistance. Therefore, by eliminating unnecessary resistance, the proportion of channel resistance, which determines the modulation of the channel, increases in the total resistance, leading to improvements not only in current magnitude but also in on/off ratio and transconductance determined by channel modulation. Thus, the self-aligned structure directly affects the characteristics of short-channel devices, and in this study, an efficient process was proposed and validated for easily fabricating the gate stack and spacer through the lift-off process.

Fig. 4. I-V characteristics and Trans-conductance results for (a) the structure without self-alignment; (b) the structure with the application of the self-aligned process.

IV. CONCLUSIONS

The new self-aligned fabrication method proposed in this study, utilizing the lift-off technique to form the gate stack, has demonstrated significant advantages and applicability. By reducing the thickness of the insulating layer, the thickness of the gate dielectric is also reduced, validating the practical feasibility of the process. The use of lift-off method allows for sufficient pattern retention and removal due to the thin thickness, enabling efficient manufacturing. These advantages can be utilized in various research endeavors, such as exploring different structures and channel materials in semiconductor industry for device development. It is anticipated that this novel self-aligned fabrication method presented in this study will greatly contribute to simplifying and enhancing the manufacturing process, leading to cost reduction. In particular, it can be easily applied in fields utilizing planar structures, such as 2D devices. This approach holds the potential to enhance cost and time efficiency for the direct implementation of short-channel structures in research institutions rather than in industrial settings. Thus, it holds the potential to make a significant impact on the advancement of modern semiconductor technology and future directions in device research.