PandeyMonalisa1
IslamAminul1
-
(Dept. of ECE, BIT, Mesra, Ranchi, Jharkhand, India)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Radiation tolerant, double exponential current source, write ability, SEU, Critical charge, read stability, delay
I. INTRODUCTION
Technology scaling plays a pivotal role in the designing of StaticRAMs. Due to technology
scaling the supply voltage and node capacitance are decreased and significantly influences
various aspects of Integrated Circuits (ICs) in terms of power consumption, delay,
area, read and write stability, reliability and critical charge [1,2]. StaticRAMs are utilized as cache memories, such as L1, L2, and L3, to bridge the
gap between the speed of microprocessors and main memory or DRAM [3].
In the cosmos environment, there exist numerous radiation particles which can be categorized
into three primary sources: galactic cosmic rays (GCRs), trapped particles, and solar
particle events (SPE) [4]. GCRs, consisting of 87% protons, 12% helium ions, and 1% heavy ions [5,6], represent one of the major sources of radiation particles. Ultra-high-energy particles,
including carbon ($^{12}$C) and iron ($^{56}$Fe) ions can travel in straight trajectories
over long distances before coming to a stop [7]. Linear energy transfer (LET) occurs along the trajectory of the particle, which
is characterized by localized ionization in the form of generation of electron-hole
pairs (EHPs) in the semiconductor [8]. These strike-generated electron or hole if collected by a storage node may pose
adverse consequences by flipping the stored content. The reliability of cache memory
cell is important especially in cosmos environment, where they are susceptible to
radiation particles that have the potential to disrupt the storage node (which is
called single event upset (SEU) or soft error), eventually leading to malfunction
of the memory cell [9]. Consequently, ensuring the reliability of cache memory cells is a challenging task
[10].
The physical mechanism of SEU in NMOSFET is shown in Fig. 1. It clearly explains that when a Highly Energetic Particle (HEP)strikes the semiconductor
material, it ionizes semiconductor materials to produce EHPs.These EHPs get accumulated
at the sensitive nodes(which are reverse biased). Due to the presence of reverse biased
junction at this node, a huge amount of charged particles are drifted and an additional
extra charge is collected at the sensitive node.When this accumulated charge at the
sensitive node is sufficient enough then it alters the contents of the cell that amount
of charge can be denoted as critical charge(Qc).Therefore, critical charge(Qc) can
simply be defined as the minimum amount of charge collected at the sensitive node
that can cause an upset to the cell content.It is also used as a metric while analyzing
the SEU robustness. Fig. 1 and 2 shows a negative/positive transient occurs in case of a NMOSFET’s/PMOSFET’s
sensitive node.
Fig. 1. SEU mechanism in NMOSFET resulting in a negative transient in its sensitive node.
Fig. 2. SEU mechanism in PMOSFET resulting in a positive transient in its sensitive node.
The conventional6T SRAM bit cell shown in (Fig. 3) is not radiation tolerant and hence not suitable for use in deep space applications.
In [11] authors introduced a transposable crossbar synapse memory using conventional 6Tbit
cell for neuromorphic processors at minimal area with fast read and write operation.
However, it is also suitable for use in deep space applications.
Fig. 3. 6T SRAM cell [21].
In [12,13], authors introduced a 10 transistor memory cell, i.e., QUATRO 10T memory Cell (see
Fig. 4) which exhibits more resistance to radiation effects but suffers from a high probability
of write failure. Subsequently, two other circuits, the PMOS(PS10T) and NMOS (NS10T)
stacked memory cells, were introduced.
Fig. 4. QUATRO10T SRAM cell [13].
In [14], authors proposed Quadruple Cross-Coupled storage cells (QUCCE12T) (see Fig. 5) consisted of 12 transistors which recovers from SEUs but consumes higher hold power
due to four access transistors that give additional path for bit line leakage.Moreover,
its also showsdegraded read stability. Another circuit QUCCE10T is also designed in
[14], which shows some improvement in the area overhead and read stability. However, it
is not efficient at low voltage operation and it suffers from a high write error rate.
Fig. 5. QUCCE 12T SRAM cell [14].
In [15], an enhanced version of QUATRO 10T is proposed named as Writability Enhanced WEQUATRO
structure with the combination of 12 transistors, (see Fig. 6) since it provides good writability.
Fig. 6. WEQUATRO SRAM cell [15].
Another 10 transistor structure named Radiation Hardened Memory-by-Design(RHMD10T)
was introduced which tolerates a high amount of critical charge and dissipates lower
hold power.However,it exhibits degradation in the write stability and longer write
delay due to the presence of a stacked structure and the use of PMOS a weak pull down
[16].
A pseudo-differential 12 transistor SRAM cell was introduced in [17] with low leakage, good read performance, higher read and write SNMs but with a penalty
of longer write delay. Moreover, numerous memory cells have been proposed throughout
the years. Several of them can be found in [18-29]. The main aim of these works is to further improve radiation tolerance, hold power
consumption, read ability, read/write access time, write margin, etc.
This paper proposes a 12 transistor-based memory cell that is radiation tolerant and
has better performance metrics in terms of hold power, write margin and RSNM as compared
with standard 6T, QUATRO10T, QUCCE12T and WEQUATRO memory cells.
The paper is structured into three further sections. Section II outlines the operating
principles of the proposed 12T SRAM cell. Section III assesses the design metrics
obtained from the PrimeSim HSPICE simulator. Finally, Section IV concludes the paper.
II. PROPOSED CELL
The schematic view of the proposed 12T SRAM cell is shown in Fig. 7. The cell is composed of a total of 12 transistors,which are subdivided into six
NMOS (N1-N6) and four PMOS (P1-P4) transistors, and two NMOS access transistors (AL
and AR) controlled by a word line (WL). Our proposed design consists of two storage
nodes, Q and QN, linked to bit lines, i.e., BL and BLB with two supporting nodes,
S0 and S1, which are employed for data recovery. The operation of our proposed 12T
memory cell is elucidated by considering the storage state of nodes ‘Q’ = ‘0’, ‘QN’
= ‘1’, ‘S0’ = ‘1’, and ‘S1’ = ‘0’respectively, for one state and viveversa for the
alternate state.
Fig. 7. PROPOSEDRTBD 12T.
Operative Modes: The three operative modes of the proposed circuit Hold, Read and
Write modes are explained below:
A. Hold Mode- In hold mode, the WL is set to be ground (WL=0) which disables all access
transistors AL and AR. The transistors P2, P3, N1, N4 and N5 and P1, P4, N2, N3 and
N6 are switched ‘ON’ and ‘OFF’, respectively, to hold the previous stored value.
B. Read Mode-In read mode, the WL is fixed to be (high) ‘1’ while bit lines are precharged
to ‘1’ (V$_{\mathrm{DD}}$). As WL=1, it activates both the access transistors, i.e.,
AL and AR. To read ‘1’ from the cell assuming that the values stored at node ‘Q’ =‘S1’=
‘0’; ‘QN’ = ‘S0’=‘1’.The transistors N1 and N5 cause the bit line bar (BLB) to discharge
to the ground, whereas transistors N2 and N6 are switched off, resulting in an incomplete
discharge path for BL. In order to perform a read operation effectively, the sense
amplifier only needs to detect a potential difference of 50 mV between BL and BLB.When
performing a read operation, a voltage bump may occur at node Q. If this voltage bump
exceeds a certain threshold level, then the cell content may flip, resulting in read
upset. To prevent read failures, it is important to properly size the transistors.
Additionally, transistors N1/5 and N2/6 should be sized stronger than AL/AR. Timing/simulated
voltage waveform during read operation of the proposed RTBD 12T memory cell is shown
in shown in Fig. 8.
Fig. 8. Timing diagram /simulated voltage waveform during read operation of the proposed RTBD 12T memory cell.
C. Write Mode- In write mode, to change the stored data, wordline is fixed to be ‘1’
and it will activate AL and AR while BL and BLB are fixed to ‘0’ and ‘1’. When BL
is grounded, node QN, which stores a '1', starts discharging through access transistor
AR, causing decrease in voltage. This impacts transistors P1 and N1, and if the voltage
of QN drops below the threshold voltage of N1, N1 turns OFF and P1 turns ON, flipping
node Q to '1'. Furthermore, node Q is charged by BLB through access transistor AL,
which enhances the flipping process.
As node Q is now '1', transistor P3 turns OFF, causing node S0 to stay in a high impedance
state and hold its value of '1'. Transistor P2 turns OFF and transistor N2 turns ON,
leading to further discharge of the potential at node QN. This also results in transistor
P4 turning ON, which makes node S1 unstable. However, the persistent signal from storage
node QN maintains node S1 at a high potential. This ensures that transistors N6 and
N3 turn ON and nodes QN and S0 get a complete discharge path to the ground, maintaining
a stable '0'.
The '0'-storing S0 node then switches off transistors N4 and N5, ensuring that nodes
S1 and Q hold a stable '1'. Therefore, values at all four nodes are flipped, which
results in a successful write operation. The timing diagrams/ simulated voltage waveform
at each node are shown to explain the proposed SRAM cell’s write operation(see Fig. 9).
Fig. 9. Timing diagram/ simulated voltage waveform during write operation of the proposed RTBD 12T memory cell.
1. Cell Sizing
In our proposed memory cell transistors are sized to prevent the cell's content from
flipping while performing read operation and also enabling a successful write operation.
The pull-upratio1 = (WP1/LP1)/(WAL/LAL) = (WP2/LP2)/(WAR/LAR) = 0.6 and pull up ratio2
= (WP3/LP3)/(WN3/LN3) = (WP4/LP4)/(WN4/LN4) = 0.5. The Cell ratio or $beta~ ratio$is
determined by the aspect ratio of the pull-down (PD) transistor to the access transistor.
To depict a successful read operation without flipping the content, the cell ratio
should be selected appropriately, i.e., (CR) = (W$_{\mathrm{N2}}$/L$_{\mathrm{N2}}$)/(W$_{\mathrm{AR}}$/L$_{\mathrm{AR}}$)
or (W$_{\mathrm{N1}}$/L$_{\mathrm{N1}}$)/ (W$_{\mathrm{AL}}$/L$_{\mathrm{AL}}$), and
in this case, it is set at 1.3.
2. Error Tolerance Analysis
Suppose that storage nodes ‘Q’ = ‘0’, ‘QN’ = ‘1’, ‘S0’ = ‘1’, and ‘S1’ = ‘0’, respectively.
SET at Q (‘0’ →‘1’):} If the energy particles strike at the sensitive node Q, causing
a flip from '0' to '1', transistor P2 is turned off and N2 is turned on, while QN
is not completely discharged due to the still switched-off N6 and the unaffected P4
transistor. Conversely, transistor P3 is switched off, causing node S0 to approach
a high impedance state, as transistor N3 is also off, resulting in a value of '1'.
This guarantees that transistors N5 and N4 are switched on, ensuring that S1 has a
discharge path to ground. When S1 is at '0', N6 is switched off and the potential
at QN remains above the threshold of transistor N1, providing storage node Q with
a complete discharge path to ground, enabling Q to recover its value of '0'. This
confirms that the value at storage node Q has been restored, ensuring that QN is also
set to '1'.
SET at S0 (‘1’→‘0’):} If SEU effects at the sensitive node S0 causing a flip from
'1' to '0', causing transistors N5 and N4 to turn off. Node S1 transitions into a
state of high impedance, where its value is '0', thereby ensuring that transistors
N3 and N6 remain inactive. Meanwhile, node Q remains unaltered, thereby guaranteeing
that transistor P3 continues to function, facilitating the charging of node S0 to
'1'. Consequently, transistors N5 and N4 become activated, resulting in node S1 exiting
the high impedance state and remaining at a steady value of '0'. This leads to the
preservation of the original states of all the nodes.
SET at S1 (‘0’→‘1’):} Likewise, exposure of the sensitive node S1, to a single event
transient flips its value from '0' to '1', causing transistors N6 and N3 to turn on.
When N3 is turned on, the state of node S0 becomes unstable. Nevertheless, transistor
N2 remains in the off position, thereby leaving the storage node QN unaltered, which,
in turn, has no impact on node Q. Node Q's persistent signal ensures that P3 remains
turned on, holding the value of S0 at '1'. As a result, N4 becomes activated, causing
the potential at node S1 to be discharged to the ground and maintaining its initial
state of '0'. Consequently, the turning off of transistors N6 and N3, in response
to the '0' at node S1, leads to the stabilization of node S0 and the successful recovery
from the SET.
SET at QN (‘1’→‘0’):} When the sensitive node QN experiences a flip from '1' to '0',
causing transistor P1 to turn on and transistor N1 to turn off. As a result of P4
being turned on, node Q is charged to '1', causing the value at storage node S1 to
become unstable. Since Q now has a value of '1', transistor P3 turns off, leading
to a state of high impedance at node S0. Additionally, with Q having a value of '1',
transistor P2 also turns off whileN2 becomes activated, thereby preventing any path
for charging node QN to '1'. This results in a persistent signal to transistor P4,
leading to the development of a high potential '1' at node S1 and the consequent activation
of transistors N3 and N6. As transistor N3 is activated, the potential at node S0
is discharged to the ground, bringing it to the '0' state. As a result, transistors
N5 and N4 turn off, ensuring that nodes S1 and Q hold their new data values steadily.
Furthermore, with transistor N6 being turned on, node QN is guaranteed a complete
discharge path to the ground, holding a stable value of '0'. Therefore, a voltage
transient at node QN can cause a single event upset (SEU) that completely alters the
cell content.
3. SEU Robustness Analysis
The metric known as Critical Charge (Q$_{C}$) is employed in the analysis of the robustness
of SEU. Q$_{C}$ is the minimum level of charge that can accumulate at the sensitive
node to induce an upset in the cell. A double exponential current source (shown in
Eq. (1)) has been utilized to inject charge at the sensitive nodes [15].
and
When performing simulation, we gradually increase the magnitude of exponential current
(I$_{0}$) at the node till the stored value at that node is flipped, and charge corresponding
to this I$_{0}$ is considered as the critical charge (Q$_{C}$). In the proposed cell,
nodes Q, S0 and S1 are able to successfully recover from SET whereas node QN storing
‘1’ is flipped when the magnitude of exponential current spike reaches 16 uA (which
is considered as current margin and the corresponding charge is 1.6 fC, which is called
critical charge (Q$_{C}$).
In this work, we have injected the current pulses at the sensitive nodes with the
rise time constant T$_{1}$ =150 ps and fall time constant T$_{2}$ =50 ps. On the basis
of these rise time and fall time constants, Fig. 10-13 have been obtained which show recovering of nodes Q, S0, S1 and flipping of node
QN.
Fig. 10. Recovery of node Q. Flipping of content in Q occurs from 0 to 1 due to injection of exponential current. As can be seen, it recovers its original value immediately.It could recover because the current source injected/ accumulated charge (Q0) is lower than critical charge (QC).
Fig. 11. Flipping of node QN. As can be seen, it is unable to recover its original value or flipping of its content occurs from 1 to 0 due to exponential current exceeding the current margin or the current source injected/ accumulated charge (Q0) is higher than critical charge (QC).
Fig. 12. Recovery of node S0 from ‘1 to 0’ transient induced due to injection of double exponential current. It could recover because the current source injected/ accumulated charge (Q0) is lower than critical charge (QC).
Fig. 13. Recovery recovery of node S1 from ‘0’ to ‘1’ transient induced due to injection of double exponential current. It could recover because the current source injected/ accumulated charge (Q0) is lower than critical charge (QC).
SEU sensitivity of all SRAM cells has been compared in Table 1 which includes critical charge (Q$_{C}$), current margin (I$_{\mathrm{O}}$), SEU
tolerance and resilience and number of sensitive nodes in the compared cells.
Table 1. SEU sensitivity comparison of all SRAM cells
|
Cell
|
QC
|
IO
|
SEU
Tolerance
|
SEU
Resilience
|
Sensitive
Nodes
|
|
6T SRAM
|
1.4 fC
|
14 ua
|
No
|
No
|
2
|
|
QUATRO 10T
|
2.0 fC
|
20 ua
|
Yes
|
No
|
4
|
|
QUCCE 12T
|
2.8 fC
|
28 ua
|
Yes
|
Yes
|
4
|
|
WEQUATRO
|
3.0 fC
|
30 ua
|
Yes
|
No
|
4
|
|
Proposed 12T
|
1.6 fC
|
16 ua
|
Yes
|
Yes
|
4
|
SNU tolerance refers to the ability of at least one node in an SRAM cell to withstand
Single Node Upsets (SNU), ensuring that the SRAM cell retains the correct stored state
even when an SNU occurs on that particular node. On the other hand, SNU resilience
implies that all nodes within the cell are capable of tolerating SNU events, and all
affected nodes can restore to their original states [30].
III. SIMULATION RESULTS & DISCUSSIONS
To evaluate the performance of a newly introduced art circuit RTBD 12T, circuit-level
simulations were conducted using a 16-nm CMOS predictive technology model developed
by the Nanoscale Integration and Modeling (NIMO) Group at Arizona State University
(ASU). The technology generation utilized in this study features a nominal supply
voltage (V$_{\mathrm{DD}}$) of 0.7 V, a nominal temperature of 25℃ and a nominal oxide
thickness (t$_{\mathrm{OX}}$) of 0.7 nm. For the purpose of estimating different design
metrics, the supply voltage (V$_{\mathrm{DD}}$), temperature (Temp) and oxide thickness
(T$_{\mathrm{OX}}$) were varied by ${\pm}$10% around its nominal value and observed
results are plotted to facilitate graphical analysis. To validate the proposed design,
extensive simulations were performed using PrimeSim HSPICE of Synopsys. The outcomes
of our proposed RTBD 12T memory cell are compared with several prior art circuits,
namely conventional 6T, QUATRO 10T, QUCCE 12T, and WEQUATRO memory cells. All the
comparisons are based on standard design metrics including Read and write delay, power
consumption, RSNM, write marginand area consumption.
Table 2 depicts the comparison of various design metrics such as read delay (T$_{\mathrm{RA}}$),
write delay (T$_{\mathrm{WA}}$), hold power (H$_{\mathrm{PWR}}$), write margin (WM)
and RSNM at nominal supply voltage (V$_{\mathrm{DD}}$) of 0.7 V, room temperature
of 25℃ and nominal oxide thickness of 0.7 nm.
Table 2. Comparison of various design metrics
|
Memory Cell
|
TRA
(ps)
|
TWA
(ps)
|
HPWR
(nW)
|
WM
(mV)
|
RSNM
(mV)
|
|
6T SRAM
|
13.53
|
25.35
|
41.52
|
286.8
|
60
|
|
QUATRO10T
|
16.46
|
287.3
|
73.56
|
87.39
|
75
|
|
QUCCE 12T
|
12.03
|
21.33
|
157.8
|
305.1
|
85
|
|
WEQUATRO
|
14.28
|
24.12
|
85.42
|
276.1
|
100
|
|
Proposed 12T
|
19.62
|
26.39
|
63.39
|
279.3
|
120
|
1. Read Access Time(TRA) or Read Delay
The duration for the read access time of memory is determined by measuring the time
elapsed between the instant when the word line (WL) goes high and when the BL or BLB
discharges to 50-mV from its precharged value (V$_{\mathrm{DD}}$). This voltage differential
is sufficient for the sense amplifier to successfully perform a read operation. This
read access time mainly depends on read current and bit-line capacitance [31].
Fig. 14 shows the comparison of read delay (T$_{\mathrm{RA}}$) by varying supply voltage
from 630 to 770 mV at room temperature of 25℃ and at nominal oxide thickness of 0.7
nm. It can be seen from the plotted figure that the T$_{\mathrm{RA}}$ of the proposed
SRAM cell is 1.45${\times}$, 1.19${\times}$, 1.63${\times}$, and 1.37${\times}$ longer
as compared to traditional 6T, QUATRO 10T, QUCCE 12T, and WEQUATRO, respectively.
Fig. 14. Read Access Time (TRA) variation w.r.t supply voltage at room temperature of 25℃ and at oxide thickness of 0.7 nm.
Fig. 15 and 16 show the comparison of read delay by varying temperature from -55 to 100℃
and oxide thickness (T$_{\mathrm{OX}}$) varied from 0.63 to 0.77 nm for the comparison
of the proposed 12T with 6T, QUATRO 10T, QUCCE 12T, and WEQUATRO memory cells. It
can be observed from the plotted figure that the T$_{\mathrm{RA}}$ of the proposed
memory cell is 1.45${\times}$, 1.19${\times}$, 1.63${\times}$, and 1.37${\times}$
longer than compared memory cells, respectively. The read delay of proposed 12T is
longer because it has a longer read path (e.g., BLB discharges through AL, N1 and
N5 and BL discharges through AR, N2 and N6). Whereas the comparison circuits have
shorter read paths consisting of only two transistors.
Fig. 15. Read Access Time (TRA) variation w.r.t temperature at nominal voltage 0.7V and at oxide thickness of 0.7 nm.
Fig. 16. Read Access Time (TRA) variation w.r.t. Oxide Thickness at room temperature of 25℃ and at nominal voltage 0.7V.
2. Write Access Time(TWA) or Write Delay
Write delay can be estimated as the time interval from the instant when word line(WL)
is activated and to the point of time when the QN node storing ‘’0’’ is raised to
supply voltage (V$_{\mathrm{DD}}$).Write delay is calculated during the write operation.
Fig. 17 shows the comparison of write access time (T$_{\mathrm{WA}}$) by varying supply voltage
from 630 to 770 mV at room temperature of 25℃ and at a nominal oxide thickness of
0.7 nm. It can be seen from the plotted figure that the write delay of proposed 12T
exhibits approximately 10.88${\times}$shorter T$_{\mathrm{WA}}$ than QUATRO 10T but
1.04${\times}$, 1.23${\times}$, and 1.09${\times}$ longer as compared to 6T, QUCCE
12T and WEQUATRO SRAM cells, respectively.
Fig. 17. Write Access Time (TRA) variation w.r.t. supply voltage at room temperature of 25℃ and at nominal oxide thickness of 0.7 nm.
Fig. 18 and 19 depict the estimated write delay with the temperature variation from -55℃
to 100℃ and process (T$_{\mathrm{OX}}$) variations from 0.63nm to 0.77 nm of proposed
12T, 6T, QUATRO 10T, QUCCE 12T, and WEQUATRO memory cells. It can be observed from
the plotted figure that the T$_{\mathrm{WA}}$ of the proposed 12T SRAM cell is1.04${\times}$,
1.23${\times}$, and 1.09${\times}$ longer as compared to 6T, QUCCE 12T and WEQUATRO
SRAM cells. Due to the presence of two pairs of access transistors QUCCE12T and WEQUATRO
is faster than proposed 12T during write operation. Our proposed circuit exhibits
approximately 10.88${\times}$shorter T$_{\mathrm{WA}}$ than QUATRO 10T. The access
MOSFETs of QUATRO-10T have a W/L ratio of 16 nm/16 nm, while that of proposed 12T
is 24 nm/16 nm.
Fig. 18. Write Access Time (TWA) variation w.r.t. temperature at nominal voltage 0.7V and at oxide thickness of 0.7 nm.
Fig. 19. Write Access Time (TWA) variation w.r.t oxide thickness at room temperature of 25℃ and at nominal voltage 0.7V.
3. Hold Power
The hold power metric is crucial when designing an SRAM cell, as cells are often in
hold mode, where the word line is disabled, and the bit line(BL and BLB) are precharged
to supply voltage for optimal delay and data retention. Power consumption is calculated
by multiplying the supply voltage (V$_{\mathrm{DD}}$) with average current (I$_{\mathrm{avg}}$).
Fig. 20 illustrate the variation of hold power (H$_{\mathrm{PWR}}$) w.r.t supply voltage
at room temperature of 25℃ and at nominal oxide thickness of 0.7 nm, while varying
VDD from 630 mV to 770 mV.It depicts that the power consumption of proposed 12T is
0.74${\times}$, 0.40${\times}$, and 0.86${\times}$ lower than WEQUATRO, QUCCE 12T
and QUATRO 10T, respectively, but 1.52${\times}$ higher H$_{\mathrm{PWR}}$ than 6T
SRAM cell because 6T consists of less number transistors as compared to proposed 12T,
WEQUATRO QUCCE 12T and QUATRO 10T.
Fig. 20. Hold Power (HPWR) variation w.r.tsupply voltage at room temperature of 25℃ and at nominal oxide thickness of 0.7 nm.
Fig. 21 and 22 depict that the power consumption of proposed 12T is 0.74${\times}$, 0.40${\times}$,
and 0.86${\times}$ lower than WEQUATRO, QUCCE 12T and QUATRO 10T, respectively. This
higher power consumption in QUCCE12T and WEQUATRO cells is due to the four access
transistors that provide additional paths for bit line leakage.Whereas the proposed
RTBD 12T consumes lower hold power because of only two access transistors. Plotted
figures show the comparison of power consumption among the proposed 12T, 6T, QUATRO
10T, QUCCE 12T,and WEQUATRO with variation of temperature from -55 to 100 $^{\circ}$C
and variation of oxide thickness (T$_{\mathrm{OX}}$) from 630 to 770 nm.
Fig. 21. Hold Power (HPWR) variation w.r.t temperature at nominal voltage 0.7V and at oxide thickness of 0.7 nm.
Fig. 22. Hold Power (HPWR) variation w.r.t oxide thickness at room temperature of 25℃ and at nominal voltage 0.7V.
4. Read Stability Analysis
The static noise margin (SNM) metric assesses the memory cell’s stability. The minimum
voltage required at the storage node to flip the cell’s state is defined as the static
noise margin of a memory cell [21]. When SNM is estimated during read operation, it is stated as RSNM.
It is measured by connecting Q and QN nodes to N1 and N2 voltage sources and varying
themsimulating the read operation. The graph plotted between two storage nodes form
a ``butterfly curve''. It determines the stability of SRAM cell during read operation.
The side length of the largest square that can be fitted in the smallest wing of the
butterfly curve gives the RSNM. Fig. 23 illustrates an example of a butterfly curve to estimate RSNM of the proposed 12T
along with 6T, QUATRO 10T, QUCCE 12T and WEQUATRO. We can observe that RSNM of proposed
12T is 2${\times}$, 1.6${\times}$, 1.4${\times}$, and 1.2${\times}$ higher than that
of 6T, QUATRO 10T, QUCCE 12T and WEQUATRO SRAM cells, respectively.
Fig. 23. Comparison of RSNM (butterfly curve method).
5. Write Ability Comparison
Write ability of the SRAM cell is gauged by the write margin(WM) and it is a prominent
method to obtain the SRAM’s write ability [32]. Write Margin is calculated by measuring the potential difference between V$_{\mathrm{DD}}$
and WL during the flipping of storage node Q and QN in a write operation. Fig. 24 illustrate the variation of write margin with respect to supply voltage at room temperature
of 25$^{\mathrm{^{\circ}}}$C and at nominal oxide thickness of 0.7 nm which depicts
that the write margin of the proposed 12T cell is 3${\times}$, 1.01${\times}$ higher
than that of other conventional circuits like QUATRO 10T, and WEQUATRO SRAM cell,
respectively, but 1.21${\times}$, 1.09${\times}$ lower than that of 6T and QUCCE 12T,
respectively.
Fig. 24. Comparison of SRAM cells in terms of write marginat different supply voltages (VDD) at room temperature of 25℃ and at nominal oxide thickness of 0.7 nm.
While executing a write operation, Combined Word Line Margin (CWLM) is estimated and
the estimated result shows that the memory cell having the lower pull-up ratio (=pull-up/access)
shows higher CWLM. The pull-up ratio (PR) and cell ratio (CR) have been compared in
Table 3. All the analyses have been done by varying V$_{\mathrm{DD}}$ from 630 mV to 770
mV, temperature from -55$^{\circ}$C to 100 $^{\circ}$C and oxide thickness from 0.77
nm to 0.63~nm (see Fig. 24-26).
Table 3. Transistor Ratio Comparison
|
Transistors
Ratio
|
6T
|
QUATRO
10T
|
QUCCE
12T
|
WE QUATRO
|
Proposed 12T
(This work)
|
|
Pull up ratio (PR)
PR-1 and
PR-2
|
0.5
|
1 and
2.2
|
1
|
1 and
0.6
|
0.6 and
0.5
|
|
Cell Ratio (CR)
|
1.3
|
1.5
|
1.8
|
1.5
|
1.6
|
Fig. 25. Comparison of SRAM cells in terms of write margin at different temperature at nominal voltage 0.7V and at oxide thickness of 0.7 nm.
Fig. 26. Comparison of SRAM cells with variation w.r.t oxide thickness at nominal voltage 0.7V and at room temperature 25℃.
6. Area Comparison
We conducted a area comparison by creating layouts of various SRAM cells and shown
in Fig. 27-31. The proposed 12T SRAM cell takes lesser area than WEQUATRO and QUCCE 12T because
the transistor size of our proposed 12T memory cell is smaller than other comparison
memory cells.
Fig. 27. Layout of Traditional 6T SRAM cell.
Fig. 28. Layout of QUATRO 10T.
Fig. 29. Layout of QUCCE 12T SRAM cell.
Fig. 30. Layout of WEQUATRO.
Fig. 31. Layout of Proposed 12T.
7. Electrical Quality Metric (EQM)
Higher Critical charge (Q$_{C}$) is the most desirable design metric of a StaticRAM
for its application in radiation hazard environments such as satellite space or surrounding
of nuclear reactors. Other critical design metrics of SRAM cell are Read Static Noise
Margin (RSNM) (or read stability) and Write Margin (or write ability), standby or
hold power (H$_{\mathrm{PWR}}$), silicon area (occupied by a cell), Read Access Time
(T$_{\mathrm{RA}}$), and Write Access Time (T$_{\mathrm{WA}}$). Generally, design
metrics of an SRAM cell are conflicting in nature. In other words, improvement in
one design metric may be achieved on the expense of (i.e., degradation of) other design
metrics. For example, RSNM (or read stability) and Write Margin (or write ability),
Critical charge (Q$_{C}$), T$_{\mathrm{RA}}$ and T$_{\mathrm{WA}}$ can be improved
by raising supply voltage (i.e., V$_{\mathrm{DD}}$). However, use of a higher supply
voltage (i.e., V$_{\mathrm{DD}}$) results in higher dynamic (i.e., Read and Write
power) and static power (i.e., H$_{\mathrm{PWR}}$) consumption. Moreover, Critical
charge (Q$_{C}$) can be improved by up sizing of MOSFETs used in the circuits, which
requires larger silicon area (which consequently increases the standby or hold power
(H$_{\mathrm{PWR}}$). Therefore, it is imperative to propose a figure-of-merit (FoM)
with which the SRAM cell can be assessed as the best. Hence, we have proposed an Electrical
Quality Metric (EQM) as figure-of-merit (FoM), which uses major design metrics including
No. of Tolerant Nodes. The used EQM is given by:
Table 4 shows the comparison of the proposed 12T with other prior memory cells using the
proposed figure-of-merit (FoM). As can be observed from Table 4 that our proposed 12T SRAM cell exhibits the highest value of EQM, proving its superiority
to other comparison SRAM cells.
Table 4. Comparison of EQM
|
Cell
|
EQM
|
|
QUATRO 10T
|
0.05
|
|
QUCCE 12T
|
3.98
|
|
WEQUATRO
|
3.19
|
|
Proposed 12T
|
4.08
|
IV. CONCLUSION
In this study, the suggested design (referred to as the proposed 12T SRAM cell) demonstrates
robust resilience at three of its four internal nodes against radiation-induced upsets,
while maintaining a critical charge (Q$_{\mathrm{C}}$) level of 1.6 fC. The proposed
12T SRAM cell shows higher read stability than that of other referenced memory cells.
Furthermore, our proposed memory cell exhibits higher write stability than QUATRO
10T and WEQUATRO and lower hold power consumption compared to WEQUATRO, QUCCE 12T
and QUATRO 10T. Finally, the overall performance metric,i.e., EQM of the proposed
12T memory cell is higher than QUATRO 10T, WEQUATRO and QUCCE 12T memory cells. Hence,
the proposed design is more suitable for operating in radiation-sensitive environments.
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Monalisa Pandey received her BTech degree in electronics and communication engineering
from A.K.T.U, Uttar Pradesh, India in 2014 and MTech degree in electronics and communication
engineering from the Abdul Kalam Technical University (AKTU) Lucknow, India, in 2018
and pursuing PhD from Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India.
Corresponding author E-mail: monalisapandey123@gmail.com
Aminul Islam received his B.Tech. degree in Computer Engg. from IE(I), in 2001, M.Tech.
degree in ECE from BIT, Mesra, in 2006 and Ph.D. degree from AMU, India, in 2013.
His areas of interest are VLSI/CAD design for emerging technologies. He has authored/co-authored
more than 306 publications on refereed journals (119), conferences (138), chapters
in Springer book (49) and 4 Indian Patents including 20 research papers in IEEE Transactions.
Dr. Islam received the best paper award eleven times in international conferences.
He is recipient of the IET Premium Best Paper Awards 2020 for paper titled “Design
and development of memristor-based RRAM’, Volume 13, Issue 4, July 2019, p. 548-557”,
He once again received the IET Premium Best Paper Awards 2021 for paper titled “Design
and development of memristor-based RRAM”, Volume 13, Issue 4, July 2019, p. 548-557”.
He is also recent of Distinguished Alumni Award from IEI Alumni Association. E-mail:
aminulislam@bitmesra.ac.in