1. The Background of the PAM-4 Receiver with Time-based LSB Decoder
Fig. 1(a) shows a conventional PAM-4 decoder, which requires three data samplers to make a
data decision. As shown in Fig. 1(b), the time-based PAM-4 decoder uses two samplers to perform the data decision [4].
Fig. 2 shows PAM-4 signaling based on gray coding. When the ratio of level mismatch (RLM)
is 1, adjacent data levels are spaced 1X apart. When the LSB is 0, the voltage difference
in PAM-4 differential signaling is 3X.
When the LSB is 1, the voltage difference is 1X. If the threshold voltage is set to
the central of the top eye (TH$_{\mathrm{P}}$), and the central of the bottom eye
(TH$_{\mathrm{N}}$), the threshold voltage difference is 2X.
In the case of the time-based LSB decoder, the LSB is determined using the relationship
that the input amplitude and the delay of the sampler are inversely proportional.
For example, if the LSB is 0, the voltage difference of the data is 3X and the threshold
voltage difference is 2X. Therefore, in the time-based LSB decoder of Fig. 3, A node is charged first. By the positive feedback with cross-coupled, the decision
of the LSB is performed. Conversely, if the LSB is 1, B node is charged first and
the decision of the LSB is performed. After the LSB decision, A and B nodes are initialized
through the reset signal for the next LSB decision.
Fig. 1. The structure of PAM-4 decoder: (a) a conventional PAM-4 decoder; (b) a time-based PAM-4 decoder.
Fig. 2. The voltage difference according to PAM-4 signaling.
Fig. 3. The structure of the time-based LSB decoder.
2. Proposed PAM-4 Decoder with Dual-mode Threshold Voltage using Time-based LSB Decoder
Fig. 4 shows the proposed PAM-4 receiver with dual-mode threshold voltage using the time-based
LSB decoder. The equalization is performed with a 2-stage CTLE, and the reduced gain
is compensated with VGAs. A total of four samplers are used in one slice: two samplers
for data decision, one edge sampler for clock and data recovery (CDR) operation, and
one error sampler for threshold voltage adaptation. A PLL-based clock and data recovery
architecture has been implemented, and to reduce clock jitter, it transmits only the
central crossing edge information of PAM-4 signaling. The threshold voltage [REF$_{\mathrm{P}}$,
REF$_{\mathrm{N}}$] for the decision of the LSB can be applied either [D$_{\mathrm{LEV3}}$,
D$_{\mathrm{LEV1}}$] or [D$_{\mathrm{LEV0}}$, D$_{\mathrm{LEV2}}$] through the external
Mode signal. The mode is determined externally by observing the V$_{\mathrm{DCM}}$
generated by the resistor divider in the last stage of the AFE and the data levels
through threshold voltage adaptation. The threshold voltage adaptation uses the MSB
value and the output of the error sampler to find the adaptive threshold voltage.
In the case of the time-based LSB decoder, the decision of the LSB is performed using
the output delay of the sampler with data input and the output delay of the sampler
with threshold input. And the delay of the sampler has the following characteristics.
1. Input amplitude and the delay of the sampler are inversely proportional [4].
2. Input common-mode voltage and the delay of the sampler are inversely proportional
[9].
When applying the threshold voltage [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] to [TH$_{\mathrm{P}}$,
TH$_{\mathrm{N}}$], the common-mode voltage of the data and the common-mode voltage
of the threshold are the same.
In the case of the proposed PAM-4 receiver, the data levels are used as the threshold
voltage. Therefore, the common-mode voltage of data and the common-mode voltage of
threshold are different. As shown in Fig. 5(a), if [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] is [D$_{\mathrm{LEV3}}$, D$_{\mathrm{LEV1}}$],
it has a higher common-mode voltage than the common-mode voltage of data. As shown
in Fig. 5(b), if [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] is [D$_{\mathrm{LEV2}}$, D$_{\mathrm{LEV0}}$],
it has a lower common-mode voltage than the common-mode voltage of data.
Fig. 6 shows an applied 2-input strong-arm latch. For a differential structure, the transconductance
remains relatively constant after the tail current source enters saturation [8]. Therefore, even when the data levels are applied as the threshold voltages, the
gm variation of the sampler is small within the range that ensures saturation region
of the tail current source. In other words, the sampler has robustness to voltage
variation [4].
Fig. 7 models the delay characteristics of the sampler with respect to the input common-mode
voltage and input amplitude. The delay of the sampler is not linear with respect to
the input amplitude, so applying [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] to [TH$_{\mathrm{P}}$,
TH$_{\mathrm{N}}$] results in a delay of the sampler that is less than the midpoint,
as shown in Fig. 7(a).
When [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] is [D$_{\mathrm{LEV3}}$, D$_{\mathrm{LEV1}}$],
the common-mode voltage of the threshold increases, resulting in a smaller delay of
the sampler. Therefore, as shown in Fig. 7(b), the delay of the sampler is relatively to the left of the case of [TH$_{\mathrm{P}}$,
TH$_{\mathrm{N}}$]. When [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] is [D$_{\mathrm{LEV2}}$,
D$_{\mathrm{LEV0}}$], the common-mode voltage of the threshold decreases and the delay
of the sampler increases. As shown in Fig. 7(b), the delay of the sampler is relatively to the right of the case of [TH$_{\mathrm{P}}$,
TH$_{\mathrm{N}}$].
Fig. 8(a) shows a test-setup for the BER schematic simulation according to threshold voltages.
As shown in Fig. 8(b), the input data is a pseudorandom binary sequence (PRBS)-7 pattern with jitter$_{\mathrm{rms}}$
of 1.2 ps, the common-mode voltage of data, D$_{\mathrm{CM}}$ is 850 mV, and the amplitude
of data, V$_{\mathrm{amp}}$ is 0.2 V. The threshold voltage is optimized as shown
in Fig. 8(c). Fig. 8(c) shows the threshold voltage, [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] applied [TH$_{\mathrm{P}}$,
TH$_{\mathrm{N}}$], [D$_{\mathrm{LEV3}}$, D$_{\mathrm{LEV1}}$] and [D$_{\mathrm{LEV2}}$,
D$_{\mathrm{LEV0}}$] respectively. The initial D$_{\mathrm{CM}}$ and REF$_{\mathrm{CM}}$
are the same. The samplers are strong arm latches, as shown in Fig. 6, with an additional parasitic capacitance of 2 fF added to the output nodes (OUT$_{\mathrm{P}}$,
OUT$_{\mathrm{N}}$) of each sampler. To consider transient noise, the Noise F$_{\mathrm{max}}$,
the Noise F$_{\mathrm{min}}$ are set to [10 GHz, 1]. The LSB is determined by the
time-based LSB decoder. Then, BER Checker was used to simulate and compare the BER
with different threshold voltages.
Fig. 9 shows the BER of LSB schematic simulation result for the common-mode voltage variation
of data. As shown in Fig. 10(a), when the common-mode voltage of data increases, the delay of the sampler with input
data decreases. However, when the input common-mode voltage of the sampler increases
and leaves the saturation region, and conversely, the delay of the sampler increases.
The input driver of the sampler enters the triode region, and the delay of the sampler
increases. A bit error occurs first when the [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$]
applied [D$_{\mathrm{LEV3}}$, D$_{\mathrm{LEV1}}$] with smallest delay of the sampler
when the common-mode voltage of data increases.
On the other hand, if the common-mode voltage of data decreases as shown in Fig. 10(b), the delay of the sampler with input data increases. Therefore, the [REF$_{\mathrm{P}}$,
REF$_{\mathrm{N}}$] applied [D$_{\mathrm{LEV2}}$, D$_{\mathrm{LEV0}}$], having the
longest delay of the sampler, it has the best BER performance.
Fig. 11 shows the BER of the LSB schematic simulation result for the common-mode voltage
variation of threshold while the common-mode voltage of the data remains at 850 mV.
As shown in Fig. 12(a), when the common-mode voltage of the threshold increases, the delay of the sampler
with the threshold decreases. However, if the input common-monde voltage is too high,
the input driver of the sampler enters the triode region, and the delay of the sampler
increases. Therefore, even if the common-mode voltage of threshold increases, the
effect on the BER performance is small in all threshold cases.
As shown in Fig. 12(b), as the common-mode voltage of thresholds decreases, the delay of the sampler increases.
Therefore, [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] applied [D$_{\mathrm{LEV3}}$,
D$_{\mathrm{LEV1}}$], having the smallest delay of the sampler, has the best BER performance.
When the analog front-end (AFE) has excessive gain due to PVT variation, the size
of the middle eye increases and the size of the top and bottom eyes decrease, as shown
in Fig. 13(b). Therefore, the BER test was performed by decreasing the size of the top and bottom
eyes in the same proportion as the middle eye size increased. The BER of LSB when
RLM is reduced by excessive gain is shown in Fig. 14.
Ideally, when RLM is 1, the voltage difference of data with LSB of 1 is 1X. However,
if the middle eye-height increases due to the excessive gain of the AFE, the voltage
difference at LSB 1 increases more than 1X, which reduces the delay of the sampler
as shown in Fig. 15. Therefore, the [REF$_{\mathrm{P}}$, REF$_{\mathrm{N}}$] with the smallest delay
in Fig. 15 is [D$_{\mathrm{LEV3}}$, D$_{\mathrm{LEV1}}$], which has the best BER performance.
Fig. 4. The structure of the proposed 20-Gb/s PAM-4 receiver with threshold voltage adaptation (quarter rate case).
Fig. 5. The voltage difference according to the data level: (a) [DLEV3, DLEV1]; (b) [DLEV2, DLEV0].
Fig. 6. The structure of Strong-arm latch.
Fig. 7. The modeling of the delay of the sampler using threshold voltage: (a) [THP, THN]; (b) [DLEV3, DLEV1] and [DLEV2, DLEV0].
Fig. 8. Test-setup for the BER schematic simulation of LSB using each threshold voltages: (a) test-setup for the BER of LSB; (b) input data: PAM-4 signaling; (c) threshold voltage.
Fig. 9. Bit Error Rate of LSB schematic simulation with common-mode voltage variation of data.
Fig. 10. The modeling of the delay of the sampler: when the common- mode voltage of data: (a) increases; (b) decreases.
Fig. 11. Bit Error Rate of LSB schematic simulation with common-mode voltage variation of threshold.
Fig. 12. The modeling of the delay of the sampler: when the common-mode voltage of threshold: (a) increases; (b) decreases.
Fig. 13. Eye diagrams when the AFE has excessive gain: (a) RLM =1; (b) RLM = 0.7
Fig. 14. Bit Error Rate of LSB schematic simulation with RLM distortion causing excessive gain of the AFE.
Fig. 15. The modeling of the delay of the sampler when the AFE has excessive gain.
4. PLL-based Clock and Data Recovery
In the proposed receiver, the threshold voltage adaptation is performed after the
PLL-based CDR is locked, enabling accurate data determination after the appropriate
threshold voltage is converged.
Fig. 17 shows the applied PLL-based CDR structure. The bottom is a conventional charge pump
phase-looked loop (CP-PLL) that receives the reference clock, which is the output
of the crystal oscillator, as an input. The top is a clock and data recovery loop
that receives data input and acquires a phase. For the VCO, it generates an 8-phase
clock using a 4-stage ring oscillator of [10]. After achieving frequency lock through the PLL, the transmission of PLL loop information
is halted, and the transmission of information for phase acquisition through the CDR
loop starts. To achieve high-speed operation, a Bang-Bang phase detector (BBPD) structure
is employed in the phase detector.
For PAM-4 signaling, in which there are four data levels per one unit interval (1UI),
there are three minor transitions, one major transition, and two intermediate transitions.
If a conventional zero-crossing CDR is employed, the non-uniform edge distribution
could lead to increased jitter [11,12]. As a result, only the crossing edge information at the center is transmitted to
generate P_UP and P_DN signals for phase acquisition. Therefore, in the proposed receiver,
before the initial threshold voltage adaptation is completed, the threshold voltage
is located at the common mode voltage of the data, allowing the transmission of information
for all transitions. After the completion of threshold voltage adaptation, only the
crossing edge information is transmitted, resulting in a reduction of clock jitter.
6. Analysis of Proposed Threshold Voltage Adaptation
The proposed threshold voltage adaptation is performed based on random data. Therefore,
the adaptation time is determined by the data pattern required during each state process.
To estimate the average time of the proposed threshold voltage adaptation, it is analyzed
based on the following assumptions.\begin{enumerate}[1.]
1. The probability of occurrence of D$_{\mathrm{LEV0}}$, D$_{\mathrm{LEV1}}$, D$_{\mathrm{LEV2}}$,
and D$_{\mathrm{LEV3}}$ is 1/4 each.
2. Each PAM-4 symbol level exhibits on the Gaussian distribution.
Table 1 shows the equations for the average adaptation time of each state. B$_{\mathrm{X}}$
is the bit value that forms the voltage of the X-level. Tcheck is the time to observe
512 data symbols to determine the current state. ${\upalpha}$ is a weight value between
approximately 2 and 4 to calibrate the adaptation time based on simulation results.
For State1, it needs D$_{\mathrm{LEV3}}$ and D$_{\mathrm{LEV2}}$ to find the top of
all the data. During the State1, if Error$_{\mathrm{LEV}}$ is located between D$_{\mathrm{LEV2}}$
and D$_{\mathrm{LEV1}}$, the Up signal generates depending on the occurrence of D$_{\mathrm{LEV3}}$
and D$_{\mathrm{LEV2}}$. After that, if Error$_{\mathrm{LEV}}$ is located between
D$_{\mathrm{LEV3}}$ and D$_{\mathrm{LEV2}}$, the Up signal is generated depending
on the occurrence of D$_{\mathrm{LEV3}}$. Therefore, the average adaptation time of
State1 is equal to (1).
In the case of State2, it needs D$_{\mathrm{LEV3}}$ and D$_{\mathrm{LEV2}}$ to find
the top of the middle eye. Initially, the Down signal is generated depending on the
occurrence of D$_{\mathrm{LEV3}}$ and D$_{\mathrm{LEV2}}$. When Error$_{\mathrm{LEV}}$
is located between D$_{\mathrm{LEV3}}$ and D$_{\mathrm{LEV2}}$, Down signal is generated
depending on the occurrence of D$_{\mathrm{LEV2}}$. Therefore, the average adaptation
time of State2 is given by Eq. (2).
Fig. 19 shows the histogram of the threshold voltage adaptation time for 10,000 runs. Since
it is based on random data, the adaptation time has a Gaussian distribution. When
the eye-height interval of single-ended data is 50 mV and the DAC resolution is 4
mV per 1 LSB, the average adaptation time is 705 ns, with a 1\% error from the equation
compared to the calculated value. If the randomness of the data cannot be ensured,
the adaptation time may become longer. To address this, specific training data patterns
might be required.
Table 1. The analysis of proposed threshold voltage adaptation