I. INTRODUCTION

Recently, brain-inspired neuromorphic computing system is gaining great deal of attention as a scalable architecture that outperforms the conventional ones in challenging tasks such as recognition, classification, and perception which usually require high parallelism in data processing ^[1,2]. For the applications necessitating real-time responsivity, the computer system should continue evolution in terms of compactness, energy efficiency, and data processing cost. Human brain is known to be highly energy-efficient and ultra-light computing system that can be benchmarked in device and circuit renovations towards the goal. Spiking neural network (SNN) provides an effective behavioral model for the human brain, which necessitates synaptic devices and neuron circuits for implementation as an electronic system ^[3-5]. Synaptic devices based on field-effect transistor (FET) structure and operation principles, and can be relatively easily integrated with the CMOS neuron circuits ^[6]. Also, emerging memory devices can be employed for synaptic devices with higher synapse array density and further Si processing compatibility is exploited ^[7-12]. The integrate-and-fire (I&F) neuron circuits are integrated with large array of synaptic devices to realize compact and energy-efficient hardware SNN ^[13-16]. An I&F neuron circuit generally integrates small currents onto a capacitive component until a threshold is reached ^[17-21]. As the voltage on the membrane capacitor exceeds the threshold, a digital pulse is generated, fired, and the synaptic weights are modulated. Then, the neuron circuit comes back to a rest. For the higher circuit and system-level simulations, modeling the synaptic devices and neuron circuits should be essential ^[22,23].

In this work, we make an alteration of a typical complementary metal-oxide-semiconductor (CMOS) neuron circuit for higher compactness. Towards this goal, the size of shunt capacitor is controlled and the effects are closely investigated in terms of I&F behaviors through series of HSPICE simulations. Also, the effects of fluctuation in input current on the response characteristics of the neuron circuit are further studied.

II. NEURON CIRCUIT DESIGN

1. Design Criteria

An I&F neuron circuit schematically shown in Fig. 1 has been designed and simulated by HSPICE. It was assumed that the circuit could be fabricated based on 0.35-${\mu}$m Si CMOS technology. BSIM3 model at level 49 (version 3.1) was used throughout the simulation works. The model parameters describing the MOSFETs implemented by the 0.35-${\mu}$m technology node were included in the circuit simulation: threshold voltage, channel mobility, gate oxide capacitance, and internal parasitic resistances and capacitances of the MOSFETs. The effects of line resistance were not considered since the neuron circuit was designed and analyzed in the stand-alone manner, and the effects of line resistances might not be so critical compared with those in the operations of high-density synapse array. The width and length of the n- and p-type MOSFETs were W = 0.35 ${\mu}$m and L = 0.70 ${\mu}$m, respectively, with the drive voltage (V$_{\mathrm{DD}}$) of 1.0 V. The membrane capacitance (C$_{\mathrm{mem}}$) was set to 0.01 pF. The input current per event was presumed to be 10 pA. The neuron circuit is made up of two parts: one is integrate-and-reset part and the other is trigger-and-fire one. C$_{\mathrm{mem}}$ is responsible for integration of the current signals from the synapse array and has the controllability over firing frequency since the value is the indication of how fast the capacitor is charged. Also, C$_{\mathrm{mem}}$ is closely related with W and L of the NMOSFET (M6) for reset operation of the neuron circuit. The integration is carried out by C$_{\mathrm{mem}}$ as current signals from the synapse array are repeatedly delivered to the neuron. As the integration progresses, the membrane potential (V$_{\mathrm{mem}}$) increases. When V$_{\mathrm{mem}}$ exceeds the threshold voltage (V$_{\mathrm{th}}$) of the NMOSFET (M1), M1 is turned on, by which the high potential at node 1 becomes low. Then, the output node of inverter 1 (INV1) is switched from low to high state, which allows M6 to be turned on and discharge the membrane capacitor completely. The potential at the output node of inverter 2 (INV2) also controls the PMOSFET (M5) before returning to its original state. The rest NMOSFETs (M2 and M3) and PMOSFET (M4) exist for stabilization of respective node states of the neuron circuit. The secondary or shunt capacitor (C$_{\mathrm{s}}$) is usually found in the previous reports as shown in Fig. 1 ^[24]. The membrane capacitor is indispensable but the shunt capacitor might be optional for realizing the I&F function to operate an SNN. It is found that in previous reports that there can be reasons to employ the secondary capacitor other than signal stability ^[24,25], such as controllability over spike width and delay. However, for compactness of the neuron circuit, it can be removed safely without a significant loss of functionality. By modulating the size of shunt capacitor, higher compactness can be acquired, which is crucial in implementing a hardware-oriented SNN chip.

Fig. 1. Schematic of the simulated neuron circuit with the indication of location of shunt capacitor, the design variable.

2. Circuit Operation

The I&F operations of a designed neuron circuit without the shunt capacitor are shown in Fig. 2(a) and (b). V$_{\mathrm{mem}}$ can be expressed in a simple mathematical relation as shown in Eqs. (1) and (2).

(1)

$ I_{in}\cdot t_{pulse}=\Delta V_{mem}\cdot C_{mem} $

(2)

$ \Delta V_{mem}=\frac{I_{in}\cdot t_{pulse}}{C_{mem}} $

Here, I$_{\mathrm{in}}$ and t$_{\mathrm{pulse}}$ are magnitude and width (duration at the top; not the period) of the input current pulse, respectively. The results in Fig. 2(a) and (b) were obtained under the condition that I$_{\mathrm{in}}$ = 10 pA, t$_{\mathrm{pulse}}$ = 0.1~ms, and C$_{\mathrm{mem}}$ = 0.01 pF. By inserting these values in Eq. (2), the increment in V$_{\mathrm{mem}}$ per pulse is obtained to be 0.1 V. The integration is continued until V$_{\mathrm{mem}}$ reaches the V$_{\mathrm{th}}$ of M1, and once V$_{\mathrm{mem}}$ exceeds the threshold, an output spike is generated at the output node of INV1 as depicted in Fig. 2(b). At the same time, C$_{\mathrm{mem}}$ is discharged by M6 and the initial state of the neuron circuit is established (reset). V$_{\mathrm{spk}}$ (firing spike voltage) is the voltage of an output signal and becomes the input signal that modulates the weight of a post-neuron synapse. It is revealed that I&F operations are realized without C$_{\mathrm{s}}$.

Fig. 2. Transient analysis results from the designed I&F neuron circuit. (a) Input current and V$_{\mathrm{mem}}$ vs. time. (b) Spike firing at the output node of the neuron circuit. }

III. EFFECTS OF THE SECONDARY CAPACITOR

Although it has been demonstrated that C$_{\mathrm{s}}$ can be optional in making up an I&F neuron circuit, for realizing the I&F operation, the effects of C$_{\mathrm{s}}$ can be further investigated. Fig. 3 shows the variation in V$_{\mathrm{spk}}$ as a function of C$_{\mathrm{s}}$. C$_{\mathrm{mem}}$ was set to 0.01 pF and the variation was checked for 20 ms, a long enough time compared with t$_{\mathrm{pulse}}$. Smaller C$_{\mathrm{s}}$ implies that the capacitive coupling between M5 gate and ground is weaker in dealing with a periodically changing signal. As C$_{\mathrm{s}}$ goes smaller, the fluctuation in V$_{\mathrm{spk}}$ becomes larger. On the other hand, larger C$_{\mathrm{s}}$ has an effect of reducing the fluctuation. Thus, it is revealed that there is a trade-off relation between area effectiveness of the neuron circuit and stability in generating identical pulses. Also, the effects of C$_{\mathrm{mem}}$ on neuron circuit have been investigated for the input current pulse with magnitude of 10 pA and duration of 20 ms. It was found that C$_{\mathrm{mem}}$ is negatively correlated with the number of spikes as shown in Fig. 4. This is due to the fact that a larger C$_{\mathrm{mem}}$ requires a longer charging time, which makes a longer time for V$_{\mathrm{mem}}$ to reach threshold voltage as also can be confirmed by Eq. (2). As the result, as C$_{\mathrm{mem}}$ gets larger, the number of firing spikes decreases as shown in Fig. 4.

Number of firing spikes of the designed I&F neuron circuit depends on the amplitude and pulse width of the I$_{\mathrm{in}}$. This dependency of the number of firing spikes is depicted in Fig. 5 and 6. The amount of time for V$_{\mathrm{mem}}$ to reach the triggering threshold voltage decreases either as the I$_{\mathrm{in}}$ pulse width becomes wider or as the amplitude gets larger. Wider I$_{\mathrm{in}}$ pulse increases the number of firing spikes of the I&F neuron circuit as shown in Fig. 5(a). Low inference current is essential for designing a highly energy-efficient hardware SNN system. The inference current in the order of a few picoamperes can be found in the flash memory synaptic devices based on poly-Si channel, and thus, the designed neuron circuit can be suited to the flash SNN architecture. The number of firing spikes increases from 1 to 8 within 10 ms as the current pulse width increases from 0.08 ms to 0.18 ms by an increment of 0.02 ms at an fixed I$_{\mathrm{in}}$ amplitude of 10 pA. Also, the number of firing spikes increases from 3 to 30 within a time window of 10 ms as the amplitude of I$_{\mathrm{in}}$ increases from 10 pA to 50 pA by an increment of 10 pA, at a fixed I$_{\mathrm{in}}$ pulse width and period of 0.1 ms and 10 ms, respectively, as shown in Fig. 5(b). It is explicitly revealed that the adjustment of frequency and amplitude of the input current practically controls the number of firing spikes as depicted in Fig. 6 in which the results in Fig. 5(a) and (b) are summarized. Power and energy consumption analyses are also important factors in designing a neuron circuit, particularly when it comes to one for SNN. The power and energy consumption for the designed I&F neuron circuit per a unit I&F function were calculated to be 1.06 ${\mu}$W and 3.04 nJ, respectively.

Fig. 3. Change in spike voltage as a function of C$_{\mathrm{s}}$.}

Fig. 4. Number of output spikes from the designed neuron circuit as a function of C$_{\mathrm{mem}}$. }

Fig. 5. Number of firing spikes as a function of time within 10-ms test window (current amplitude = 10 pA) for (a) different I$_{\mathrm{in}}$ pulse intervals within 10-ms test window (interval is varied from 0.08 ms to 0.18 ms by an increment of 0.02 ms) and for (b) different I$_{\mathrm{in}}$ amplitudes varied from 10 pA to 50 pA by an increment of 10 pA (pulse width = 0.1 ms and period = 10 ms).

Fig. 6. Number of firing spikes as a function of time width and amplitude of the I$_{\mathrm{in}}$ pulse. }

IV. CONCLUSION

In this work, we have designed and characterized an I&F neuron circuit truncating the shunt capacitor in the conventional neuron circuit, through series of HSPICE simulations, presuming the 0.35-${\mu}$m CMOS technology. The overall frame of the circuit is based on an existing one but one of the major capacitors has been removed aiming higher area efficiency. Functions of the individual capacitors have been closely investigated, with a particular interest in the relation between membrane capacitance and spiking frequency. The results in this work describe how an I&F neuron circuit might properly behave depending on synaptic device parameters in the SNN hardware specifically designed for maximizing the parallelism in data-intensive decision making and would suggest a way to expect higher area efficiency in designing CMOS neuron circuits.