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1. (School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea)
2. (Research and Development Center, Samsung Display, Yongin 17113, Korea)

Indium-gallium-zinc oxide (IGZO), thin-film transistors (TFTs), quantitative analysis, channel width, self-heating stress

## I. INTRODUCTION

Since the invention of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) in 2004 by Prof. Hosono and coworkers, IGZO TFTs have attracted considerable attention because of their superior properties including high electron mobility, excellent on/off ratio, low process temperature, and high uniformity [1-4]. These merits render IGZO TFTs particularly suitable for applications in high-resolution organic light emitting diode (OLED) displays [5]. To utilize IGZO TFTs for pixel and gate driver circuits in OLEDs, they should possess high current capability because the drivers will need to handle currents of hundreds of milliamperes on each output [6,7]. To increase the current capability of IGZO TFTs, it is necessary to increase their channel width. Therefore, it is very important to study the effects of channel width on the electrical stability of IGZO TFTs. Previously, some studies have been conducted on the effects of channel width on the electrical stability of IGZO TFTs, especially under self-heating stress (SHS) conditions [8-10]. These studies revealed that the degree of degradation was more significant under SHS conditions in IGZO TFTs with increased channel width. This was mainly attributed to the enhanced self-heating effects in TFTs with a wider channel width, originating from the low thermal conductivity of the IGZO [11]. However, most of these previous studies only analyzed the self-heating effects qualitatively. For example, the dominant degradation mechanism enhanced by the self-heating effects was attributed to one of two mechanisms: electron/hole trapping in the gate dielectric or changes in the subgap density of states (DOS) in the active region [12,13]. However, since several degradation mechanisms of different origins can cause stress-induced electrical performance degradation in IGZO TFTs, it is very important to analyze degradation caused by self-heating quantitatively in IGZO TFTs. In this study, we examined the effects of channel width on electrical performance degradation in commercially-available top-gate self-aligned (TG-SA) coplanar IGZO TFTs under SHS. Furthermore, we comprehensively investigated the quantitative contribution of every degradation mechanism that caused the SHS-induced threshold voltage shift (${\Delta}$V$_{\mathrm{TH}}$) in IGZO TFTs with different channel widths.

## II. EXPERIMENTAL DETAILS

The IGZO TFTs used in this study had a TG-SA coplanar structure and were fabricated using the following process. First, an oxide buffer layer was deposited on a polyimide substrate using plasma-enhanced chemical vapor deposition (PECVD). Then, an IGZO layer (In:Ga:Zn = 1:1:1 at \%) was deposited by radio-frequency magnetron sputtering.

Subsequently, a SiO$_{\mathrm{X}}$ layer was deposited by PECVD as a gate dielectric, followed by the deposition of a gate metal (Molybdenum). After deposition and patterning of the gate electrode and gate dielectric, SiO$_{\mathrm{X}}$ and SiN$_{\mathrm{X}}$ were deposited as an interlayer dielectric (ILD) by PECVD and patterned to form via holes. The via-contact-type n$^{+}$-IGZO source (S) and drain (D) electrodes of Al were then deposited and patterned. Finally, the devices were thermally annealed at 300 $^{\circ}$C in air to achieve stable and uniform electrical performance. The fabricated device is schematically illustrated in Fig. 1. The bias stress experiments were performed on IGZO TFTs with a width (W)/length (L) of 30/5 ${\mu}$m and 50/5 ${\mu}$m. The electrical characterizations were conducted using an Agilent 4156C parameter analyzer. The SHS condition used in this experiment was a gate-to-source voltage (V$_{\mathrm{GS}}$) of 30 V, a drain-to-source voltage (V$_{\mathrm{DS}}$) of 10 V, and a recovery condition of V$_{\mathrm{GS}}$ = V$_{\mathrm{DS}}$ = 0 V at room temperature in a dark environment.

## III. RESULTS AND DISCUSSION

Fig. 2(a) and (b) display the time dependencies of the transfer curves measured at V$_{\mathrm{DS}}$ = 0.1 V under SHS for IGZO TFTs with W/L = 30/5 and 50/5 ${\mu}$m, respectively, while Fig. 2(c) and (d) respectively display the transconductances (g$_{\mathrm{m}}$ = ${\mu}$$_{\mathrm{FE}}$${\cdot}$C$_{\mathrm{OX}}$${\cdot}V_{\mathrm{DS}}$${\cdot}$W/L). Here, ${\mu}$$_{\mathrm{FE}} is the field-effect mobility and C_{\mathrm{OX}} is the gate dielectric capacitance per unit area. Fig. 2 demonstrates that the transfer curve shifted in the positive direction and g_{\mathrm{m}} (and {\mu}$$_{\mathrm{FE}}$) increased with increasing stress time in both TFTs. In addition, the degree of transfer curve shift and ${\Delta}$g$_{\mathrm{m}}$ (and ${\Delta}$${\mu}$$_{\mathrm{FE}}$) were larger in the TFT with W/L = 50/5~${\mu}$m.

Fig. 3(a) and (b) display the time dependencies of the transfer curves in the saturation region (V$_{\mathrm{DS}}$ = 15 V) measured from the IGZO TFT with W/L = 30/5 ${\mu}$m under SHS in the forward and reverse modes, respectively, while Fig. 3(c) and (d) respectively display the dependencies of the IGZO TFT with W/L = 50/5 ${\mu}$m. Here, the definitions of source and drain are the same as in the stress condition in the forward mode, although the source and drain are interchanged in the reverse mode. The experimental results in Fig. 3 suggest that the ${\Delta}$V$_{\mathrm{TH}}$ values were larger in the TFT with W/L = 50/5 ${\mu}$m both operation modes, where V$_{\mathrm{TH}}$ is defined in this study as the value of V$_{\mathrm{GS}}$ inducing a drain current (I$_{D}$) of W/L ${\times}$ 10 nA. Fig. 3 also indicates that ${\Delta}$V$_{\mathrm{TH}}$ extracted from the forward mode characterization was larger than that extracted from the reverse mode characterization in both TFT dimensions.

This result demonstrates that the local V$_{\mathrm{TH}}$ exhibited different values after SHS in both TFTs.

Fig. 4(a) and (b) display the small signal C$_{GS}$-V$_{GS}$ and C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curves measured at a frequency of 50 kHz from the IGZO TFT with W/L = 30/5 ${\mu}$m before and after SHS was applied for 2100 s, respectively, while Fig. 4(c) and (d) respectively display the same curves for the TFT with W/L = 50/5 ${\mu}$m. Here, C$_{\mathrm{GS}}$ and C$_{\mathrm{GD}}$ represent the gate-to-source and gate-to-drain capacitance obtained with a floating drain and source electrode, respectively. The experimental results in Fig. 4 indicate that the capacitance-voltage (C-V) curves shifted in the positive direction and stretched out after SHS in both TFTs. However, it should be stated that these phenomena were more significant in the TFT with W/L = 50/5 ${\mu}$m. Fig. 4 also demonstrates that the degree the curve stretched out after SHS was more significant in the C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curve than in the C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curve in both TFTs.

The experimental results in Fig. 2-4 clearly demonstrate that the degradation in electrical performance of the fabricated TG-SA coplanar IGZO TFT under SHS was more significant in the TFT with the wider channel width. This result is consistent with the results from previous studies and has been attributed to enhanced self-heating effects [13,14]. From Fig. 2-4, it is also evident that the electrical performance of the TFTs was nonuniformly degraded along the channel length direction. This implies it is necessary to investigate the quantitative contribution of every degradation mechanism that causes SHS-induced ${\Delta}$V$_{\mathrm{TH}}$ in the source and drain sides.

The stretched out of the C-V curve observed after SHS in the fabricated IGZO TFT in Fig. 4 indicates that the subgap DOS increased after SHS. Therefore, to conduct a quantitative analysis of SHS-induced electrical performance degradation in IGZO TFTs with different channel widths, we first extracted the subgap DOS from both IGZO TFTs before and after SHS near the source and drain sides, respectively. The subgap DOS was extracted using the optical charge pumping method [15,16], where the C$_{\mathrm{GS}}$-V$_{\mathrm{GS}}$ and C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curves were used to extract the subgap DOS near the source and drain sides of the IGZO TFTs, respectively. The C-V curves were measured using an LCR meter (HP4284A) with a 50 kHz ac signal. Here, we used a 3-mW illumination source with a wavelength corresponding to a photonic energy of 2.4 eV. Furthermore, we obtained the energy distribution of the subgap DOS profile from the V$_{GS}$-dependent capacitance data [17,18]. Fig. 5(a) displays the energy distribution of the subgap DOS extracted from both IGZO TFTs near the source side before and after applying SHS for 2100 s, while Fig. 5(b) displays the distribution near the drain side of the devices. The extracted subgap DOS (g(E)) was divided into four components according to their distribution shapes in energy level: the densities of acceptor-like tail states (g$_{\mathrm{TA}}$), acceptor-like deep states (g$_{\mathrm{DA}}$), shallow donor states (g$_{\mathrm{SD}}$), and oxygen-related defect states (g$_{\mathrm{O}}$) in the energy gaps of the IGZO TFTs. We modeled the extracted subgap DOS near E$_{C}$ as follows:

##### (1)
\begin{aligned} & g(E)=g_{T A}(E)+g_{D A}(E)+g_{S D}(E)+g_O= \\ & N_{T A} \exp \left(-\frac{E_C-E}{k T_{T A}}\right)+N_{D A} \exp \left(\left(-\frac{E_C-E_{D A}}{k T_{D A}}\right)^2\right)+N_{S D} \exp \left(\left(-\frac{E_C-E_{S D}}{k T_{S D}}\right)^2\right) \\ & +N_O \exp \left(\left(-\frac{E_C-E_o}{k T_O}\right)^2\right) \end{aligned}

which is denoted by the lines in Fig. 5. In Eqn. (1), E is the electron energy, N$_{\mathrm{TA}}$ is the density of trap states extrapolated to E$_{C}$, kT$_{\mathrm{TA}}$ is the characteristic energy of the acceptor-like states, k is the Boltzmann constant, N$_{\mathrm{DA}}$/N$_{\mathrm{SD}}$ /N$_{\mathrm{O}}$ are the Gaussian acceptor-like/donor-like/oxygen-related state densities, E$_{\mathrm{DA}}$/E$_{\mathrm{SD}}$/E$_{\mathrm{O}}$ are the Gaussian mean energies, kT$_{\mathrm{DA}}$/kT$_{\mathrm{SD}}$/kT$_{\mathrm{O}}$ are the Gaussian deviations, and E$_{C}$ is the conduction band minimum. Here, the oxygen-related defect states imply the oxygen vacancies or excess oxygen-related subgap states [19-22].

## IV. CONCLUSIONS

In this study, we conducted a quantitative analysis of the effects of channel width on SHS-induced ${\Delta}$V$_{\mathrm{TH}}$ in IGZO TFTs. The analysis was conducted using TG-SA coplanar IGZO TFTs with different channel widths (W/L = 30/5 ${\mu}$m and 50/5 ${\mu}$m) and the SHS was applied under bias conditions of V$_{\mathrm{GS}}$ = 30 V and V$_{\mathrm{DS}}$ = 10 V. By applying the subgap DOS-based ${\Delta}$V$_{\mathrm{TH}}$ decomposition technique, we concluded that ${\Delta}$V$_{\mathrm{TH}}$ under SHS in the fabricated IGZO TFTs was caused by increases in g$_{\mathrm{SD}}$ and g$_{\mathrm{DA}}$ in the IGZO thin film and electron trapping in the fast and slow traps of the SiO$_{\mathrm{X}}$ gate dielectric. However, we also observed that every ${\Delta}$V$_{\mathrm{TH}}$ originating from each degradation mechanism increased with an increase in channel width. Moreover, we concluded that the increase in ${\Delta}$V$_{\mathrm{TH}}$_$_{\mathrm{SLOW}}$ due to the higher channel temperature was the dominant reason for more significant electrical performance degradation in the fabricated IGZO TFT with a wider channel width after SHS.

## ACKNOWLEDGMENTS

This research was supported by the Chung-Ang University Research Scholarship Grants in 2022, Samsung Display Co., Ltd. and the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (2020R1A2B5B01001765).

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##### Dong-Ho Lee

Dong-Ho Lee received the B.S degree in electronic engineering from Gachon University, Gyeonggi-Do, South Korea, in 2020. Since 2020, He is currently pursuing the integrated M.S., Ph.D. degrees in electrical and electronics engineering from Chung-Ang University. His current research interest includes the reliability study of oxide thin-film transistors.

##### Hwan-Seok Jeong

Hwan-Seok Jeong received the B.S. degree in chemistry from Dae-Jin University, Pochen, South Korea, in 2015. He is currently pursuing the Ph.D. degree in electrical and electronics engineering from Chung-Ang University. His current research interest includes the fabrication and reliability study of oxide thin-film transistors.

##### Yeong-Gil Kim

Yeong-Gil Kim received the B.S. degree in electronic engineering from Seoul National University of Science and Technology, Seoul, South Korea, in 2022. He is currently pursuing the M.S. degree in electrical and electronics engineering from Chung-Ang University. His current research interest includes the fabrication and reliability study of oxide thin-film transistors.

##### Myeong-Ho Kim

Myeong-Ho Kim is a research engineer with the Research and Development Center, Samsung Display, Yongin, South Korea.

##### Kyoung Seok Son

Kyoung Seok Son is a research engineer with the Research and Development Center, Samsung Display, Yongin, South Korea.

##### Jun Hyung Lim

Jun Hyung Lim received the Ph.D. degree from the Department of Materials Science and Engineering, Sungkyunkwan University, Suwon, South Korea, in 2006. He is in charge of the oxide backplane with the Research and Development Center, Samsung Display, Yongin, South Korea.

##### Sang-Hun Song

Sang-Hun Song received his BS degree in Electronics Engineering from Seoul National University in 1886 and his MA and Ph.D. degrees from Princeton University in 1988 and 1997, respectively. His doctoral research studies on magneto-optical and magneto-transport properties of the 2- dimensional carriers in strained semiconductor layers. In 1997, he joined LG Semicon Co. Ltd. As a DRAM circuit designer. In 2001, he joined the School of Electrical and Electronics Engineering at Chung-Ang University in Seoul, where his now a professor. His research interests include semiconductor materials and devices, and their applications to real world electronic systems.

##### Hyuck-In Kwon

Hyuck-In Kwon received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, South Korea, in 1999, 2001, and 2005, respectively. From August 2004 to March 2006, he was a Research Associate with the University of Illinois at Urbana-Champaign. In 2006, he joined the System LSI Division, Samsung Electronics Company, South Korea, where he was a Senior Engineer with the Image Development Team. From September 2007 to February 2010, he was with the School of Electronic Engineering, Daegu University, as a full-time Lecturer and an Assistant Professor. Since 2010, he has been with Chung-Ang University, Seoul, where he is currently a Professor with the School of Electrical and Electronics Engineering. His research interests include CMOS active pixel image sensors, oxide thin-film transistors, and silicon nanotechnologies.