I. INTRODUCTION

Since the invention of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) in 2004 by Prof. Hosono and coworkers, IGZO TFTs have attracted considerable attention because of their superior properties including high electron mobility, excellent on/off ratio, low process temperature, and high uniformity ^[1-4]. These merits render IGZO TFTs particularly suitable for applications in high-resolution organic light emitting diode (OLED) displays ^[5]. To utilize IGZO TFTs for pixel and gate driver circuits in OLEDs, they should possess high current capability because the drivers will need to handle currents of hundreds of milliamperes on each output ^[6,7]. To increase the current capability of IGZO TFTs, it is necessary to increase their channel width. Therefore, it is very important to study the effects of channel width on the electrical stability of IGZO TFTs. Previously, some studies have been conducted on the effects of channel width on the electrical stability of IGZO TFTs, especially under self-heating stress (SHS) conditions ^[8-10]. These studies revealed that the degree of degradation was more significant under SHS conditions in IGZO TFTs with increased channel width. This was mainly attributed to the enhanced self-heating effects in TFTs with a wider channel width, originating from the low thermal conductivity of the IGZO ^[11]. However, most of these previous studies only analyzed the self-heating effects qualitatively. For example, the dominant degradation mechanism enhanced by the self-heating effects was attributed to one of two mechanisms: electron/hole trapping in the gate dielectric or changes in the subgap density of states (DOS) in the active region ^[12,13]. However, since several degradation mechanisms of different origins can cause stress-induced electrical performance degradation in IGZO TFTs, it is very important to analyze degradation caused by self-heating quantitatively in IGZO TFTs. In this study, we examined the effects of channel width on electrical performance degradation in commercially-available top-gate self-aligned (TG-SA) coplanar IGZO TFTs under SHS. Furthermore, we comprehensively investigated the quantitative contribution of every degradation mechanism that caused the SHS-induced threshold voltage shift (${\Delta}$V$_{\mathrm{TH}}$) in IGZO TFTs with different channel widths.

II. EXPERIMENTAL DETAILS

The IGZO TFTs used in this study had a TG-SA coplanar structure and were fabricated using the following process. First, an oxide buffer layer was deposited on a polyimide substrate using plasma-enhanced chemical vapor deposition (PECVD). Then, an IGZO layer (In:Ga:Zn = 1:1:1 at \%) was deposited by radio-frequency magnetron sputtering.

Subsequently, a SiO$_{\mathrm{X}}$ layer was deposited by PECVD as a gate dielectric, followed by the deposition of a gate metal (Molybdenum). After deposition and patterning of the gate electrode and gate dielectric, SiO$_{\mathrm{X}}$ and SiN$_{\mathrm{X}}$ were deposited as an interlayer dielectric (ILD) by PECVD and patterned to form via holes. The via-contact-type n$^{+}$-IGZO source (S) and drain (D) electrodes of Al were then deposited and patterned. Finally, the devices were thermally annealed at 300 $^{\circ}$C in air to achieve stable and uniform electrical performance. The fabricated device is schematically illustrated in Fig. 1. The bias stress experiments were performed on IGZO TFTs with a width (W)/length (L) of 30/5 ${\mu}$m and 50/5 ${\mu}$m. The electrical characterizations were conducted using an Agilent 4156C parameter analyzer. The SHS condition used in this experiment was a gate-to-source voltage (V$_{\mathrm{GS}}$) of 30 V, a drain-to-source voltage (V$_{\mathrm{DS}}$) of 10 V, and a recovery condition of V$_{\mathrm{GS}}$ = V$_{\mathrm{DS}}$ = 0 V at room temperature in a dark environment.

Fig. 1. Schematic illustration of fabricated TG-SA coplanar IGZO TFTs.

III. RESULTS AND DISCUSSION

Fig. 2(a) and (b) display the time dependencies of the transfer curves measured at V$_{\mathrm{DS}}$ = 0.1 V under SHS for IGZO TFTs with W/L = 30/5 and 50/5 ${\mu}$m, respectively, while Fig. 2(c) and (d) respectively display the transconductances (g$_{\mathrm{m}}$ = ${\mu}$$_{\mathrm{FE}}$${\cdot}$C$_{\mathrm{OX}}$${\cdot}$V$_{\mathrm{DS}}$${\cdot}$W/L). Here, ${\mu}$$_{\mathrm{FE}}$ is the field-effect mobility and C$_{\mathrm{OX}}$ is the gate dielectric capacitance per unit area. Fig. 2 demonstrates that the transfer curve shifted in the positive direction and g$_{\mathrm{m}}$ (and ${\mu}$$_{\mathrm{FE}}$) increased with increasing stress time in both TFTs. In addition, the degree of transfer curve shift and ${\Delta}$g$_{\mathrm{m}}$ (and ${\Delta}$${\mu}$$_{\mathrm{FE}}$) were larger in the TFT with W/L = 50/5~${\mu}$m.

Fig. 3(a) and (b) display the time dependencies of the transfer curves in the saturation region (V$_{\mathrm{DS}}$ = 15 V) measured from the IGZO TFT with W/L = 30/5 ${\mu}$m under SHS in the forward and reverse modes, respectively, while Fig. 3(c) and (d) respectively display the dependencies of the IGZO TFT with W/L = 50/5 ${\mu}$m. Here, the definitions of source and drain are the same as in the stress condition in the forward mode, although the source and drain are interchanged in the reverse mode. The experimental results in Fig. 3 suggest that the ${\Delta}$V$_{\mathrm{TH}}$ values were larger in the TFT with W/L = 50/5 ${\mu}$m both operation modes, where V$_{\mathrm{TH}}$ is defined in this study as the value of V$_{\mathrm{GS}}$ inducing a drain current (I$_{D}$) of W/L ${\times}$ 10 nA. Fig. 3 also indicates that ${\Delta}$V$_{\mathrm{TH}}$ extracted from the forward mode characterization was larger than that extracted from the reverse mode characterization in both TFT dimensions.

This result demonstrates that the local V$_{\mathrm{TH}}$ exhibited different values after SHS in both TFTs.

Fig. 4(a) and (b) display the small signal C$_{GS}$-V$_{GS}$ and C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curves measured at a frequency of 50 kHz from the IGZO TFT with W/L = 30/5 ${\mu}$m before and after SHS was applied for 2100 s, respectively, while Fig. 4(c) and (d) respectively display the same curves for the TFT with W/L = 50/5 ${\mu}$m. Here, C$_{\mathrm{GS}}$ and C$_{\mathrm{GD}}$ represent the gate-to-source and gate-to-drain capacitance obtained with a floating drain and source electrode, respectively. The experimental results in Fig. 4 indicate that the capacitance-voltage (C-V) curves shifted in the positive direction and stretched out after SHS in both TFTs. However, it should be stated that these phenomena were more significant in the TFT with W/L = 50/5 ${\mu}$m. Fig. 4 also demonstrates that the degree the curve stretched out after SHS was more significant in the C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curve than in the C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curve in both TFTs.

The experimental results in Fig. 2-4 clearly demonstrate that the degradation in electrical performance of the fabricated TG-SA coplanar IGZO TFT under SHS was more significant in the TFT with the wider channel width. This result is consistent with the results from previous studies and has been attributed to enhanced self-heating effects ^[13,14]. From Fig. 2-4, it is also evident that the electrical performance of the TFTs was nonuniformly degraded along the channel length direction. This implies it is necessary to investigate the quantitative contribution of every degradation mechanism that causes SHS-induced ${\Delta}$V$_{\mathrm{TH}}$ in the source and drain sides.

The stretched out of the C-V curve observed after SHS in the fabricated IGZO TFT in Fig. 4 indicates that the subgap DOS increased after SHS. Therefore, to conduct a quantitative analysis of SHS-induced electrical performance degradation in IGZO TFTs with different channel widths, we first extracted the subgap DOS from both IGZO TFTs before and after SHS near the source and drain sides, respectively. The subgap DOS was extracted using the optical charge pumping method ^[15,16], where the C$_{\mathrm{GS}}$-V$_{\mathrm{GS}}$ and C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curves were used to extract the subgap DOS near the source and drain sides of the IGZO TFTs, respectively. The C-V curves were measured using an LCR meter (HP4284A) with a 50 kHz ac signal. Here, we used a 3-mW illumination source with a wavelength corresponding to a photonic energy of 2.4 eV. Furthermore, we obtained the energy distribution of the subgap DOS profile from the V$_{GS}$-dependent capacitance data ^[17,18]. Fig. 5(a) displays the energy distribution of the subgap DOS extracted from both IGZO TFTs near the source side before and after applying SHS for 2100 s, while Fig. 5(b) displays the distribution near the drain side of the devices. The extracted subgap DOS (g(E)) was divided into four components according to their distribution shapes in energy level: the densities of acceptor-like tail states (g$_{\mathrm{TA}}$), acceptor-like deep states (g$_{\mathrm{DA}}$), shallow donor states (g$_{\mathrm{SD}}$), and oxygen-related defect states (g$_{\mathrm{O}}$) in the energy gaps of the IGZO TFTs. We modeled the extracted subgap DOS near E$_{C}$ as follows:

which is denoted by the lines in Fig. 5. In Eqn. (1), E is the electron energy, N$_{\mathrm{TA}}$ is the density of trap states extrapolated to E$_{C}$, kT$_{\mathrm{TA}}$ is the characteristic energy of the acceptor-like states, k is the Boltzmann constant, N$_{\mathrm{DA}}$/N$_{\mathrm{SD}}$ /N$_{\mathrm{O}}$ are the Gaussian acceptor-like/donor-like/oxygen-related state densities, E$_{\mathrm{DA}}$/E$_{\mathrm{SD}}$/E$_{\mathrm{O}}$ are the Gaussian mean energies, kT$_{\mathrm{DA}}$/kT$_{\mathrm{SD}}$/kT$_{\mathrm{O}}$ are the Gaussian deviations, and E$_{C}$ is the conduction band minimum. Here, the oxygen-related defect states imply the oxygen vacancies or excess oxygen-related subgap states ^[19-22].

Table 1 presents the subgap DOS parameters extracted from both IGZO TFTs near the source and drain electrodes before and after SHS. From Fig. 5 and Table 1, it is evident that g$_{\mathrm{SD}}$ increased after SHS in both devices, although the increase was more significant in the TFT with the wider channel width, especially near the drain side. This increase in the g$_{\mathrm{SD}}$ after SHS could be attributed to hydrogen diffusion from the source/drain IGZO metallization region (n$^{+}$-IGZO region) to the IGZO channel region. Hydrogen becomes a shallow donor, generating free electrons in ZnO-based oxide semiconductors ^[23,24]. Therefore, it increases g$_{\mathrm{SD}}$ and facilitates the formation of a percolation conduction path in the IGZO. Moreover, because the channel temperature increases with an increase in channel width (due to enhanced self-heating effects), hydrogen diffusion accelerates more with increased channel width. The higher concentration of the hydrogen within the channel caused higher g$_{\mathrm{SD}}$ and gm (and ${\mu}$$_{\mathrm{FE}}$) after SHS in the IGZO TFT with the wider channel width, as observed in Fig. 5 and 2, respectively. The larger increase in the g$_{\mathrm{SD}}$ near the drain side of the TFT after SHS could be attributed to the higher channel temperature during SHS near the drain side of the TFT. This originated from the lower electron concentration and higher channel resistivity causing a higher level of Joule heating during SHS. Fig. 5 and Table 1 also demonstrate that g$_{\mathrm{DA}}$ only increased after SHS in the TFT with the wider channel width (W/L = 50/5 ${\mu}$m), which could be ascribed to the generation of an M-OH bond facilitated by the higher channel temperature ^[25-27]. The experimental results in Fig. 5 and Table 1 clearly indicate that the channel width strongly affected the local generation of subgap states under SHS in IGZO TFTs.

Electron trapping in the gate dielectric is another phenomenon that was enhanced by the self-heating effects under SHS. In this study, we used the subgap DOS-based ${\Delta}$V$_{TH}$ decomposition technique [23, 28, 29] to extract the electron trapping-induced ${\Delta}$V$_{TH}$ from both IGZO TFTs after SHS near the source and drain sides. From the experimental results in Fig. 5, we assumed that the physical mechanisms responsible for ${\Delta}$V$_{TH}$ under SHS in the fabricated IGZO TFTs were increased g$_{\mathrm{SD}}$ and g$_{\mathrm{DA}}$ in the IGZO active region and electron trapping in the fast and slow traps in the SiO$_{\mathrm{X}}$ gate dielectric. Here, the fast/slow trap implies the electronic trap state in the gate dielectric located relatively close to/far from the interface with a lower/higher energy barrier for detrapping.

Fig. 6(a) illustrates the decomposition scheme of ${\Delta}$V$_{\mathrm{TH}}$ into the contributions of each mechanism, where t$_{\mathrm{STR}}$ and t$_{\mathrm{REC}}$ are the stress and the subsequent recovery time during an application of the subgap DOS-based ${\Delta}$V$_{\mathrm{TH}}$ decomposition technique, respectively. Here, ${\Delta}$V$_{\mathrm{TH \_ SD}}$ and ${\Delta}$V$_{\mathrm{TH \_ DA}}$ are the ${\Delta}$V$_{\mathrm{TH}}$ values caused by increases in g$_{\mathrm{SD}}$ and g$_{\mathrm{DA}}$, respectively, and ${\Delta}$V$_{\mathrm{TH \_ FAST}}$ and ${\Delta}$V$_{\mathrm{TH \_ SLOW}}$ are the ${\Delta}$V$_{\mathrm{TH}}$ values caused by electron trapping into the fast and slow traps, respectively. As reported, the donor-like state becomes positively charged if the Fermi level is below it and is neutral when the trap is occupied (i.e., the Fermi level is above). However, the acceptor-like state is neutral if the Fermi level is below it and is negatively charged when the trap is occupied (i.e., the Fermi level is above) ^[30]. Therefore, ${\Delta}$V$_{\mathrm{TH\_ SD}}$/${\Delta}$V$_{\mathrm{TH \_ DA}}$ adopt negative/positive values in this study and can be calculated as

Here, q is the elementary charge of an electron, t$_{\mathrm{IGZO}}$ is the active layer thickness, and E$_{\mathrm{F}}$ is the Fermi level at the flat-band condition. Fig. 6(b) and (c) display the SHS-induced ${\Delta}$V$_{\mathrm{TH \_ SD}}$ and ${\Delta}$V$_{\mathrm{TH \_ DA}}$ values extracted near the source and drain sides from IGZO TFTs with W/L = 30/5~${\mu}$m and 50/5 ${\mu}$m, respectively. In Fig. 6(a), V$_{\mathrm{TH}}$ recovery after termination of SHS was mainly due to electron-detrapping from the fast trap in the gate dielectric. Therefore, ${\Delta}$V$_{\mathrm{TH \_ FAST}}$ could be obtained directly by using the subgap DOS-based ${\Delta}$V$_{\mathrm{TH}}$ decomposition technique schematically illustrated in Fig. 6. Then, ${\Delta}$V$_{\mathrm{TH \_ SLOW}}$ is calculated using

where ${\Delta}$V$_{\mathrm{TH \_ TOTAL}}$ is the ${\Delta}$V$_{\mathrm{TH}}$ value measured from the time dependence of the transfer curve under SHS at a specific stress time.

Fig. 7(a) and (b) display the time evolution of ${\Delta}$V$_{\mathrm{TH}}$ during SHS and recovery phases extracted in the forward and reverse operation modes from the IGZO TFTs with W/L = 30/5 ${\mu}$m and 50/5 ${\mu}$m, respectively. Figs. 7(c) and (d) summarize the ${\Delta}$V$_{\mathrm{TH}}$ values originating from each degradation mechanism after the application of SHS for 2100 s extracted near the source and drain sides of the IGZO TFTs with W/L = 30/5 ${\mu}$m and 50/5 ${\mu}$m, respectively. Figs. 7(c) and (d) indicate that the ${\Delta}$V$_{\mathrm{TH}}$ values from every degradation mechanism increased as the channel width increased. However, the increase in the ${\Delta}$V$_{\mathrm{TH \_ SLOW}}$ was the dominant reason for the more significant electrical performance degradation of the IGZO TFT with a wider channel width. Given that the higher channel temperature in the TFT with a wider channel width was caused by enhanced Joule heating effects, this is consistent with the experimental results in the previous study, where trapped electrons transferred more easily to deeper positions within the gate dielectric by Poole-Frenkel conduction with an increase in temperature ^[31,32]. Figs. 7(c) and (d) also demonstrate that ${\Delta}$V$_{\mathrm{TH \_ TOTAL}}$, ${\Delta}$V$_{\mathrm{TH \_ SLOW}}$, and ${\Delta}$V$_{\mathrm{TH \_ FAST}}$ exhibited higher values near the source side of the TFT. This could be attributed to the higher vertical electric fields under SHS near the source side, even though the channel temperature was higher near the drain side during SHS.

Fig. 2. Time dependence of transfer curves measured at V$_{\mathrm{DS}}$ = 0.1 V under SHS from IGZO TFTs with (a) $W/L = 30/5$ ${\mu}$m; (b) 50/5 ${\mu}$m. Time dependence of the transconductance (g$_{\mathrm{m}}$ = ${\mu}$$_{\mathrm{FE}}$${\cdot}$$_{\mathrm{OX}}$${\cdot}$V$_{\mathrm{DS}}$${\cdot}$W/L) measured at V$_{DS}$ = 0.1 V under SHS from IGZO TFTs with (c) W/L = 30/5 ${\mu}$m; (d) 50/5 ${\mu}$m.

Fig. 3. Time dependence of transfer curves in the saturation region (V$_{\mathrm{DS}}$ = 15 V) measured from the IGZO TFT with W/L = 30/5 ${\mu}$m in the (a) forward; (b) reverse modes under SHS. Time dependence of transfer curves in the saturation region (V$_{\mathrm{DS}}$ = 15 V) measured from the IGZO TFT with W/L = 50/5~${\mu}$m in the (c) forward; (d) reverse modes under SHS.

Fig. 4. Small signal: (a) C$_{\mathrm{GS}}$-V$_{\mathrm{GS}}$; (b) C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curves measured at a frequency of 50 kHz from the IGZO TFT with W/L = 30/5 ${\mu}$m before and after application of SHS for 2100 s. Small signal; (c) C$_{\mathrm{GS}}$-V$_{\mathrm{GS}}$; (d) C$_{\mathrm{GD}}$-V$_{\mathrm{GS}}$ curves measured at a frequency of 50 kHz from the IGZO TFT with W/L = 50/5 ${\mu}$m before and after application of SHS for 2100 s.

Fig. 5. Energy distribution of the subgap DOS extracted from IGZO TFTs with W/L = 30/5 ${\mu}$m and 50/5 ${\mu}$m near the (a) source; (b) drain sides of the IGZO TFT before and after application of SHS for 2100 s.

Fig. 6. (a) Schematic illustration of the ${\Delta}$V$_{\mathrm{TH}}$ decomposition scheme based on the subgap DOS-based ${\Delta}$V$_{\mathrm{TH}}$ decomposition technique. The ${\Delta}$V$_{\mathrm{TH \_ SD}}$ and ${\Delta}$V$_{\mathrm{TH \_ DA}}$ values were extracted near the source and drain sides after applying SHS for 2100 s from IGZO TFTs with (b) W/L = 30/5 ${\mu}$m; (c) 50/5 ${\mu}$m.

Fig. 7. Time evolution of ${\Delta}$V$_{\mathrm{TH}}$ during SHS and recovery phases extracted during forward and reverse mode operation from IGZO TFTs with (a) W/L = 30/5 ${\mu}$m; (b) 50/5 ${\mu}$m. The ${\Delta}$V$_{\mathrm{TH}}$ values originated from each degradation mechanism after applying SHS for 2100 s extracted near the source and drain sides from IGZO TFTs with (a) W/L = 30/5 ${\mu}$m; (b) 50/5~${\mu}$m.

IV. CONCLUSIONS

In this study, we conducted a quantitative analysis of the effects of channel width on SHS-induced ${\Delta}$V$_{\mathrm{TH}}$ in IGZO TFTs. The analysis was conducted using TG-SA coplanar IGZO TFTs with different channel widths (W/L = 30/5 ${\mu}$m and 50/5 ${\mu}$m) and the SHS was applied under bias conditions of V$_{\mathrm{GS}}$ = 30 V and V$_{\mathrm{DS}}$ = 10 V. By applying the subgap DOS-based ${\Delta}$V$_{\mathrm{TH}}$ decomposition technique, we concluded that ${\Delta}$V$_{\mathrm{TH}}$ under SHS in the fabricated IGZO TFTs was caused by increases in g$_{\mathrm{SD}}$ and g$_{\mathrm{DA}}$ in the IGZO thin film and electron trapping in the fast and slow traps of the SiO$_{\mathrm{X}}$ gate dielectric. However, we also observed that every ${\Delta}$V$_{\mathrm{TH}}$ originating from each degradation mechanism increased with an increase in channel width. Moreover, we concluded that the increase in ${\Delta}$V$_{\mathrm{TH}}$_$_{\mathrm{SLOW}}$ due to the higher channel temperature was the dominant reason for more significant electrical performance degradation in the fabricated IGZO TFT with a wider channel width after SHS.