Mobile QR Code QR CODE

  1. (Department of Electronic Engineering, Myongji University, Yongin 17058, Korea )
  2. (2Department of Electronic Engineering, Gachon University, Seongnam 13120, Korea)

One-transistor (1T) dynamic random-access memory (DRAM), sensing margin, technology computer-aided design (TCAD)


The conventional dynamic random-access memory (DRAM) in the one-transistor one-capacitor (1T1C) structure is reaching the scaling challenge. As scaling down, the size of the capacitor decreased, reaching the limit of data storage capability. Therefore, 1T DRAM without the capacitor is attracting the great deal of attention as a promising alternative to overcome the existing problems [1-10]. Band-to-band tunneling (BTBT) can be a plausible principle for high-speed and energy-efficient write operation [11-14], compared with impact ionization and carrier accumulation (storage) in the floating channel. However, in case of BTBT operation, it is rather difficult to a large sensing margin and long retention time. Thus, for higher competitiveness of 1T DRAM, it is essential to improve sensing margin and data retention time through efficient carrier generation and preservation capabilities. In this work, for the goals, a novel 1T DRAM with a rasied SiGe quantum well under one gate in the double-gate (DG) structure is proposed and characterized [15]. The electrical characteristic of 1T DRAM which utilize the valence band offset according to the band gap energy difference of Si and SiGe is investigated [16,17]. In this research through electrical characteristics obtained from the TCAD simulations, we compare the sensing margin of the conventional Si-based 1T DRAM with that of the proposed 1T DRAM and we also optimize the proposed 1T DRAM by comparing the Ge content and the SiGe well thickness. In the last part, a viable process integration for fabricating the optimally designed 1T DRAM cell is proposed.


Fig. 1 shows the schematic of the proposed device structure with the raised SiGe quantum well. Two-dimensional (2-D) device simulations are conducted to analyze the electrical characteristics of the 1T DRAM device using Silvaco tools. In these simulations, doping concentration dependent mobility model, band gap narrowing effect, band-to-band tunneling, Auger recombination, and Shockley-Read-Hall recombination are considered for reliable and accurate simulation results. The proposed 1T DRAM design specifications are summarized in Table 1. The optimized SiGe well height and Ge content are 40 nm and 0.3, respectively.

Fig. 2 shows an energy band between the two gates at the initial hold state. The bias condition at the hold state is at V$_{\mathrm{GS}}$= -1.0 V and V$_{\mathrm{DS}}$= 0 V. In the hold state after the write state, most of generated holes are stored in SiGe region. Since the valence band offset (VBO) properties of SiGe and Si acts as a barrier that blocks the movement of holes, the generated holes are effectively stored in the body of the proposed structure.

Table 2 shows bias condition used for 2-D simulation of 1T DRAM. In order to check the feasibility of the proposed idea, a thick gate oxide and a long channel length are used in this research, and the required voltage condition can be lowered by scaling down the size of proposed structure. The bias condition of the write operation is V$_{\mathrm{GS}}$ = -4.0 V and V$_{\mathrm{DS}}$ = 3.0 V. When a write voltage is applied, holes can be effectively generated through BTBT at the drain junction. Due to the VBO characteristics of SiGe and body Si, hole leakage can be reduced, and therefore the retention characteristics can be increased. Erase operation voltage is at V$_{\mathrm{GS}}$= 3.0 V and V$_{\mathrm{DS}}$= -3.0 V. When an erase voltage is applied, the erase operation is carried out by drawing holes stored in body and SiGe well into the drain. Also, since the SiGe well is used only under one gate, the read operation can be made less destructive and the stored holes can be effectively removed over the erase operation, which leads to improvements in sensing margin and data retention.

Fig. 1. Schematic of the proposed device structure.
Fig. 2. Energy-band diagram under the initial hold condition.
Table 1. Parameters of proposed device

Gate length

400 nm

S/D width

800 nm

S/D thickness

80 nm

Body thickness

80 nm

SiGe well thickness

40 nm

Si1-xGex content

x = 0.3

Gate oxide thickness

5 nm

S/D doping concentration

1020 cm-3

Gate doping concentration

1020 cm-3

Body doping concentration

1017 cm-3

p-type SiGe doping contatcentration

1017 cm-3

Table 2. Bias condition used for 2-D simulation of 1T DRAM






Gate voltage (V)





Drain voltage (V)





Source voltage(V)





Time (ns)






Fig. 3 shows the change in transient characteristics when raised Si well and SiGe well are used compared to conventional structures. Each operating state is maintained for 10 ns. The difference in the drain current between the read ``1'' and read ``0'' state is defined as the sensing margin and the values of the difference in the drain current between each structure are compared. The conventional structure has a Si body without Si well or SiGe well. In the conventional structure, the read ``1'' current and the read ``0'' current are 14.76 A/${\mu}$m and 7.92 A/${\mu}$m, respectively, so the sensing margin of the conventional structure becomes 6.84 A/${\mu}$m. The read ``1'' in the structure containing Si well is 19.54 A/${\mu}$m, and the read ``0'' is 7.42 A/${\mu}$m. The sensing margin of the including Si well structure becomes 12.12 A/${\mu}$m. The read ``1'' of the structure containing SiGe 40nm well is 97.78 A/${\mu}$m and the read ``0'' is 4.31 A/${\mu}$m. The sensing margin of the including SiGe well structure becomes 93.47 A/${\mu}$m.

As shown in these results, the low sensing margin of the conventional structure can be improved by utilizing the device with the SiGe well. The structure having SiGe well has a sensing margin of 86.63 A/${\mu}$m higher than the conventional structure, and is 81.35 A/${\mu}$m higher than the structure having the Si well. At the operation of write ``1'', in the proposed structure, the barrier oxide beside the SiGe well and the VBO between Si and SiGe can prevent the diffusion of the holes gathered in the body on both sides, thereby increasing the retention time. In the structure having the Si well and conventional structure, the hole diffusion occurs into the source and drain immediately after the write operation progresses. In Fig. 3, the read ``1'' current of the structure of having Si well and the conventional structure becomes low during the read operation. On the other hand, in the structure having the SiGe well, the read ``1'' current is maintained. As confirmed in these results, the diffusion of the holes is prevented by the barrier oxide and the VBO of SiGe and Si-body. Therefore, the proposed structure has better write operation properties than the conventional 1T DRAM. And it also increases the hole capacity and has a higher sensing margin.

Fig. 4 shows the change of drain current under operating conditions at different well depths. After applying the write and erase voltages, the read ``1'' and the read ``0'' currents are compared. The sensing margin at each height is 29.97 A/${\mu}$m at 5 nm height, 91.00 A/${\mu}$m at 20 nm height, and 93.47 A/${\mu}$m at 40 nm height. The sensing margin is the highest when the height of the well is 40 nm, because the space that can store the hole increases as the height of the well increases. For the optimization of the well height, the read current ratio obtained by dividing the read ``1'' current by the read ``0'' current while changing the well height from 10 nm to 70 nm is compared as shown in Fig. 5. In order to confirm the data retention characteristics, the read current ratios at hold times = 64 ms and 512 ms are also compared.

A device with a low well height does not have enough space to store the holes generated by the write operation. Therefore, it is difficult to obtain high read 1 current. On the other hand, in devices with too high well height, it is difficult to create and store holes because the gate far from the drain junction is difficult to influence in the write operation. In addition, in the erase operation, if the height of the well is too high, it is difficult to push the holes trapped in the well out of the well and pull it toward the drain. Therefore, it is important to select the optimal well height that can effectively perform write and erase operations while making enough hole storage space. The simulation results show that the devices with 40 nm height well have the highest sensing margin and the longest retention time.

Fig. 6 shows the change of the sensing margin after 64 ms hold time when the Ge content of the SiGe well varies from 0.2 to 0.5. When the Ge content is 0.3, the sensing margin is measured to be the highest with 42.95 ${\mu}$A. The bandgap energy (E$_{\mathrm{G}}$) of SiGe well decreases as the Ge content increases. In other words, the VBO between Si and SiGe increases. Therefore, as the Ge content increases, the holes are more efficiently stored in the SiGe well in the write operation, and as a result, the read ``1'' current also increases. However, if the Ge content is excessively high, the hole cannot escape from the SiGe well even after the erase operation due to VBO, and as a result, the read ``0'' current increases. For this reason, when the Ge content exceeds 0.3, the sensing margin decreases.

Operating characteristics at high temperatures are also one of the important evaluation factors of DRAM products. The short retention time at high temperature is a weakness of the conventional 1T DRAM [18]. Fig. 7 shows the retention characteristics at 300 K and 358 K of the optimized structure (40 nm height and 0.3 Ge content of the raised SiGe well). The sensing margin of 64 ms is 13.93 ${\mu}$A/${\mu}$m and the sensing margin of 128 ms is 9.436~${\mu}$A/${\mu}$m at 358 K (85$^{\circ}$C). Therefore, the proposed structure satisfies the ITRS requirement as it maintains a sensing margin of more than 6 ${\mu}$A/${\mu}$m after hold times of 64 ms and 128 ms at 85$^{\circ}$C. [19].

Fig. 3. Comparison of sensing margins among different devices.
Fig. 4. Comparison of sensing margins at different well heights.
Fig. 5. Change of read current ratio when the height of the well is changed from 10 nm to 70 nm.
Fig. 6. Change of the sensing margin when the germanium content of the SiGe well is changed from 0.2 to 0.5 after 64-ms hold.
Fig. 7. The retention characteristics at 300 K and 358 K of the optimized structure (40 nm height and 0.3 Ge content of the raised SiGe well).


The proposed structure is similar to the conventional double-gate (DG) structure. Fig. 8(a)-(e) shows the process of 1T DRAM fabrication utilizing a protruded SiGe. In the fabrication process, the device structure utilizes the buried oxide as the bottom layer for making floating body. Fig. 8(a) shows the basic substrate using silicon on insulator (SOI) wafer. In addition, a sidewall structure is made by SiN on the one side of SiO$_{2}$. Si at the bottom of this sidewall becomes the active region of the device. Fig. 8(b) shows that SiGe well is formed through epitaxy process on one side of Si after Si layer is partially etched using SiO$_{2}$ and SiN as hard masks. Fig. 8(c) shows that after removing the SiO$_{2}$ hard mask, only the SiGe well and Si active region is left. After that, a gate oxide and polysilicon gate are formed after removing the SiN sidewall (Fig. 8(d)). Finally, the proposed device fabrication is completed by removing the SiGe well located next to the source and drain regions (Fig. 8(e)).

Fig. 8. Fabrication process flow of the proposed device.


Recently, 1T DRAM has become a great alternative due to the scaling down issue of DRAM. The study was investigated to improve the low sensing margin and low retention time of conventional 1T DRAM structure. The write operation was improved by the valence band offset (VBO) using the raised SiGe quantum well (QW). In addition, since the SiGe well is used only under the one gate, the write and read operation can be made more effectively, which leads to improvements in sensing mar gin and retention characteristics. Through the TCAD simulation results, we investigated the sensing margin and retention time of the proposed structure which are better than the conventional 1T DRAM. For the optimization of the structure, the effects of the height and Ge content (x) of the well were investigated. And the proposed structure also satisfied the retention characteristics requirement for stand-alone DRAM application at 358 K. Finally, the fabrication method and the order of fabrication are also introduced.


This research was supported by the National Research Foundation (NRF) of Korea funded by the Ministry of Science and ICT (MSIT) under Grants NRF-2020R1G1A1007430 and NRF-2022M3I7A1078936. The EDA tool was supported by the IC Design Education Center (IDEC), Korea.


S. Okhonin, et al., “A Capacitor-less SOI 1T-DRAM concept,” IEEE Int. SOI Conf., pp. 153-154, 2001.DOI
T. Osawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1510-1522, 2002.DOI
C. Kuo, et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications,” IEDM Tech. Dig., pp. 843-846, Dec. 2002.DOI
S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A capacitor-less 1T-DRAM cell,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 85-87, Feb. 2002.DOI
C. Kuo, T.-J. King, and C. Hu, “A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications,” IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2408-2416, Dec. 2003.DOI
J. H. Seo, Y. J. Yoon, E. Yu, W. Sun, H. Shin, I. M. Kang, J.-H. Lee, and S. Cho, “Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM with Charge-Trap Effect,” IEEE Electron Device Lett., vol. 40, no. 4, pp. 566-569, Apr. 2019.DOI
Md. H. R. Ansari, N. Navlakha, J. Y. Lee, and S. Cho, “Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement,” IEEE Trans. Electron Devices, vol. 67, no. 4, pp. 1471-1479, Apr. 2020.DOI
Md. H. R. Ansari and S. Cho, “Performance Improvement of 1T DRAM by Raised Source and Drain Engineering,” IEEE Trans. Electron Devices, vol. 68, no. 4, pp. 1577-1584, Apr. 2021.DOI
Y. J. Yoon, J. H. Seo, S. Cho, J.-H. Lee, and I. M. Kang, “A polycrystalline-silicon dual-gate MOSFET-based 1-T DRAM using grain boundary-induced variable resistance,” Appl. Phys. Lett., vol. 114, no. 18, pp. 183503-1-183503-5, May 2019.DOI
J.-T. Lin, H.-H. Lin, Y.-J. Chen, C.-Y. Yu, A. Kranti, C.-C. Lin, and W.-H. Lee, “Vertical transistor with n-bridge and body on gate for low-power 1T-DRAM application,” IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 4937-4945, Dec. 2017.DOI
E. Yoshida and T. Tanaka, “A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006.DOI
E. Yu, S. Cho, H. Shin, and B.-G. Park, “A Band-Engineered One-Transistor DRAM with Improved Data Retention and Power Efficiency,” IEEE Electron Device Lett., vol. 40, no. 4, pp. 562-565, Apr. 2019.DOI
N. Navlakha, J.-T. Lin, and A. Kranti, “Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering,” J. Appl. Phys., vol. 119, no. 21, 214501, Jun. 2016.DOI
E. Yu, S. Cho, K. Roy, and B.-G. Park, “A Quantum-Well Charge-Trap Synaptic Transistor with Highly Linear Weight Tunability,” IEEE J. Electron Devices Soc., vol. 8, pp. 834-840, Aug. 2020.DOI
M. G. Ertosun, P. Kapur, and K. C. Saraswat, “A highly scalable capacitorless double gate quantum well single transistor DRAM: 1T-QW DRAM,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1405-1407, Dec. 2008.DOI
A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329-337, Nov. 2011.DOI
Colombo, Luciano, R. Resta, and S. Baroni, “Valence-band offsets at strained Si/Ge interfaces,” Phys. Rev. B, vol. 44, no. 11, 5572, 1991.DOI
Almeida, L. Mendes, et al., “Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM,” Solid-State Electron., vol. 90, pp. 149-154, 2013.DOI
A. Pal, A. Nainani, S. Gupta, and K. C. Saraswat, “Performance improvement of one-transistor DRAM by band engineering,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 29-31, Jan. 2012.DOI
Siwon Lee

Siwon Lee is pursing the B.S. degree in the Department of electrical engineering and receiving semicon-ductor equipment linkage major from Myongji University, Yongin.

Seongjae Cho

Seongjae Cho received the B.S. and the Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Republic of Korea, in 2004 and 2010, respectively. He worked as an Exchange Researcher at the National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan, in 2009. Also, he worked as a Postdoctoral Researcher at Seoul National University in 2010 and at Stanford University, CA, USA, from 2010 to 2013. He joined the Department of Electronic Engineering, Gachon University, Seongnam, Republic of Korea, in 2013, where he is currently working as an Associate Professor. His current research interests include emerging memory technologies, advanced nanoscale CMOS devices, group-IV photonic devices, novel memory cells for neuromorphic and processing-in-memory applications, and all-solid energy storage devices. He is a Senior Member of IEEE and a Lifetime Member of IEIE.

Il Hwan Cho

Il Hwan Cho received the B.S. in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea, in 2000 and M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2002, 2007, respectively. From March 2007 to February 2008, he was a Postdoctoral Fellow at Seoul National University, Seoul, Korea. In 2008, he joined the Department of Electronic Engineering at Myongji University, Yongin, where he is currently a Professor. His current research interests include improvement, characterization and measurement of non-volatile memory devices and nano scale transistors including tunneling field effect transistor.

Garam Kim

Garam Kim received the B. S. and the Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2008 and 2014, respectively. He worked as a senior engineer at Samsung Electronics from 2014 to 2019. In 2019, he joined the Department of Electronic Engineering at Myongji University, Yongin, where he is currently an assistant professor. His current research interests include GaN-based LEDs, tunnel FETs, neuromorphic devices, capacitor-less 1T DRAMs, nagative capacitance FETs, FinFETs, and CMOS image sensors.