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  1. (Department of Electronic Engineering at Kwangwoon University, Seoul, 139-701, Korea)
  2. (Silicon R&D Corp. Seongnam-si, Gyeonggi-do, 13510, Korea)
  3. (C4I R&D Center, LIG Nex1 Company, Seongnam-si, Gyeonggi-do, 13510, Korea)
  4. (Defense Industry Technology Center, Agency of Defense Development, Daejon-si, Chungcheong nam-do, 13510, Korea )

Ultra-wideband, CMOS, radar, through-the-wall, equivalent time sampling, time interleaved sampling


Through-the-wall radar (TWR) for the detection of human being or moving object behind the wall has been paid attentions both in military and commercial safety applications. Especially, the ultra-wideband (UWB) radar is the mostly used for the TWR due to its fine range resolution and good penetration characteristics through the various walls [1-7]. The cm-level resolution allows us to distinguish the human existence easily using the information of body movement and breathing. During the military tactical or human rescue operations, the small size and light weight are the important requirements of the portable TWR equipment for the efficient and safe mission in the various severe environments. Up to now, although many developments of TWR are published, few literatures have been presented, which deal with the small form factor and light weight TWR using the highly integrated radar IC [6,7]. Comparing with the existing hybrid radar module, the integrated UWB radar IC greatly reduces the number of the hybrid components and discrete MMICs on the PCB board and makes it possible to implement the small size and light weight radar transceiver board. Moreover, the UWB radar IC based radar consumes the smaller power than the hybrid one, enabling the longer operation time and lower weight battery.

In the view point of the penetration and propagation loss, sub-GHz UWB radar has the smaller path loss including the penetration loss so that the longer detection range through the wall can be obtained. In this paper, a TWR sensor with the highly integrated UWB radar IC is presented. The chosen UWB frequency band ranges from 0.9 to 1.5 GHz for the lower path loss and better penetration characteristics.

The digitally synthesized impulse generator for the transmitter and the equivalent time sampling receiver are adopted as in Fig. 1 [10,11]. For the resolution enhancement, the time-interleaved sampling is employed using the four parallel sampling channels, and the sampling clock for each channel is generated from the two cascaded delay locked loop (DLL) consisting of the coarse and fine clock blocks. The finally achieved timing resolution is 200 ps, which corresponds to the 3 cm range resolution. For calculating the overall link budget for the TWR, the signal attenuation through the wall is experimentally measured with the CW signal and the well-known antenna in priori. While depending on the wall material and thickness, the measured penetration loss through the concrete brick wall is about 15 dB. The radar performance is demonstrated with the radar signal processing part, which utilizes the moving target indication (MTI) and envelope detection algorithms. This paper presents the radar IC and module mainly, and also the through-wall human detection results with the aid of the basic signal processing part.

Fig. 1. Block diagram of UWB TWR radar IC.


1. UWB Radar Transceiver Architecture

Fig. 1 shows a simplified block diagram of the UWB radar transceiver which is composed of a transmitter, 4-channel receiver, and two cascaded DLLs for the sampling clock generation. The digitally controlled UWB impulse generator transmits the periodical UWB impulse waveforms, and then the receiver accepts the echo signal which has the round-trip time to the target. The received echo signal coming from the target is amplified by RF front-end amplifier stage and then splitted into the time- interleaved 4-channel analog signal processing (ASP) arrays via the active RF power splitter. In order to obtain the fast sampling rate for the high resolution, the receiver adopts both the equivalent time sampling (ETS) and the time-interleaved sampling techniques, whereas at each ASP channel the received signal is sampled with 0.2 ns interleaved clocks provided by the fine-bin DLL. Fig. 2 demonstrates how the virtually high speed sampling is achieved using ETS technique combined with the interleaved architecture. The pulse repetition time is 100 ns and the 125 times recursive samplings are done with the time shift of 0.8 ns for every sample. The clocks C1 - C125 of 0.8 ns interval are generated in the coarse-bin DLL, and in turn, four clocks F1 - F4 of 0.2 ns interval are also provided by the fine-bin DLL using Ck for 4 each channel.

For the mitigation of the DC offset noise in the ASP, which is amplified and usually saturates the ASP circuits, the 8-bit digital-to-analog converter (DAC) based DC offset calibration is used. Each receiver channel has a high-speed track-and-hold (T/H) circuit, an integrator, a sample-and-hold (S&H) circuit, and data-combining analog multiplexer (MUX) in the order. Moreover, not shown in Fig. 1, to compensate for the severe through-wall loss, the additional external PA and LNA are added for the radar gain enhancement.

Fig. 2. 4-channel time interleaved equivalent time sampling diagram.

2. High Resolution Radar Receiver Design

The RF front-end of the receiver consists of a LNA, 2-stage RF variable gain amplifier (RF VGA), an active power splitter, and track/hold circuit array for each channel. A noise cancelling common-gate common-source (CGCS) amplifier is used as the LNA both to obtain the wideband gain-noise matching and the single to differential signal conversion, as shown in Fig. 3. Since CS and CG paths have the amplitude and phase mismatches, the capacitive cross coupled structure is also adopted to reduce the mismatch and improve the noise figure. The Fig. 4(a) and (b) show the circuit schematics of the RF VGA and the 4-way (or channel) RF power splitter amplifier, respectively. The 2-stage RF VGA consists of two cascode amplifiers with the shunt CMOS transistor switch (M$_{5}$ and M$_{6}$) at the differential drain nodes of common source transistors for controlling the gain and enhance the linearity of the radar receiver. The simulated gain of the RF front end from LNA to RF VGA ranges from 16.9 dB to 37 dB at 1.2 GHz (center frequency), and the simulated NF are 3.0 and 8.6 dB for max and min gain conditions, respectively.

The amplified RF signal is equally splitted into 4 channels by the 4-way power splitter amplifier. The RF power splitter is a cascode amplifier with the four common gate transistor pairs (M$_{3}$ and M$_{4}$) for each ASP channel. The full gain and NF of the RF front end including LNA, VGA, and splitter, are 37 dB and 4.0 dB at 1.2 GHz, respectively. With the simple resistor load R$_{\mathrm{D}}$, the simulated 3 dB bandwidth is exceeding about 1.8 GHz. The fast time-varying UWB signal divided by the RF splitter is tracked and held at the T/H circuit, and amplified by the analog buffer amplifier and succeeding integrator. Fig. 5 shows the circuit schematic of the high-speed T/H circuit. The first stage of the track and hold circuit employs the shunt peaking load to extend the gain-bandwidth product. The T/H core adopts the switch source-follower structure, which allows the good linearity and the tracking bandwidth. The fast current path switching easily provides the high-speed sampling and holding performance. The required sampling clocks for each channel (track, hold, and sample) are generated by F1-F4 clocks coming from the fine-bin DLL [10].

The sampling clocks for 4-channels have the 200 ps time interval between the neighboring channels and the period of 800 ps. In order to realize the averaging and smoothing of the sampled signal, a conventional active RC integrator is employed in the radar receiver. During the averaging period, the clock number for the transmitter is not changed and the repeated sampling at the same time bin is performed. Hence the recursive sampled voltage is productively integrated so that the signal to noise ratio (SNR) is linearly improved by the number of repeated sampling times. The integration time is usually 25 us (250 integration times) and controlled by the external digital processing part. Also with the tuning of RC value of the integrator, the integrator gain can be variable from -9 dB to 45 dB. The DC gain of ASP is so large in the integrator that the amplified DC offset would be detrimental at the ASP output. Hence, 8-bit DAC is used for DC-offset correction at the input stage of analog integrator and controlled also by the digital part. The input-referred DC offset calibration range is up to 120 mV. At the final stage of ASP, the low speed S/H circuit and buffer amplifier is employed, and the integrated data is acquired and transferred to the external ADC included in the digital processing part. The DC offset mismatch between the 4-channel is compensated by individual optimization of DAC value for each channel. And addressed to the gain mismatch, the 1-dB step gain control in the integrator stage with the tunable resistor calibrates the gain of each channel and mitigates the effect of channel mismatch. The compensation with DAC and gain control is performed and optimized manually with the radar control S/W via SPI setting.

Fig. 3. Noise cancelling common-gate common-source LNA.
Fig. 4. Circuit schematic of (a) RF VGA; (b) RF power splitter.
Fig. 5. Circuit schematic of high speed T/H.

3. Radar Sampling Clock Generation using DLL

As shown in Fig. 6, in order to realize the equivalently high speed sampling or ETS, two cascaded DLLs are adopted as the timing clock generation circuit, which is locked to an external 10 MHz crystal oscillator [10]. Hence the pulse repetition interval (PRI) is 100 ns and the maximum detection range with no ambiguity is 15 m. Each DLL is composed of a voltage-controlled delay line (VCDL) cells, phase frequency detector and charge-pump with start-up circuit. The coarse-bin (CB) DLL generates 125 bin clocks (C1 - C125) with 0.8 ns interval. One of them is chosen by the bin selection MUX and used for triggering the digital impulse generator. The fine-bin (FB) DLL generates the four clocks (F1 - F4) with 0.2 ns time intervals, where C124 and C125 from the CB DLL are used as the reference clock and comparing clock, respectively. The generated four timing clocks from the FB DLL are fed to the individual T/H sampler of the four receiver channels, resulting in 0.2 ns equivalent sampling time resolution and 3 cm range resolution.

Fig. 6. Circuit schematic of high speed T/H.

4. UWB Waveform Generator

In contrast to the VCO based impulse generator, a digital pulse generator is employed due to its smaller chip size, the wider tunable range of the center frequency, and the lower power consumption [10,11]. Fig. 7 shows the simplified block diagram of the proposed pulse generator. The pulse generator consists of the variable time delay cells, D-flip/flop unit pulse generator array, a pulse combiner and shaper, and a final driver amplifier. The variable delay cell is an inverter, whose time delay is changed by controlling the current source. While the array of the delay cells provides the successively time delayed clocks to D-F/F array, the outputs from two neighboring D-F/F are injected into EX-OR and the unit pulse of duration ${\tau}$ is generated.

The center frequency is determined as 0.5${\tau}$, and the number of combined pulses decides the frequency bandwidth. Therefore, the center frequency and bandwidth are tunable by controlling the delay time and number of pulses. Considering the clock jitter noise, the source clock D(0) is coming from the DLL. If we assume that the jitter is 50 ps, the spectrum may be blurred about 500 kHz at 1 GHz center frequency, which doesn’t matter in respect of the target detection and spectrum regulation.

In order to minimize the side-lobes in frequency spectrum, a pulse shaping method is realized by the different and symmetrical amplifier gains in the pulse combiner stage, which enables the filtering and shaping of the UWB waveform without off chip filter component. And the spectrum change of the transmitter due to process and supply voltage changes are also scrutinized in the simulation. Fig. 8 shows the transmitter spectrum for each process condition (slow/typical/fast), and about 5 dB sidelobe magnitude change is observed also with the slight center frequency shift.

Fig. 7. Digitally synthesized impulse generator and output waveform.}
Fig. 8. Tx spectrum change due to process variation.}


The UWB radar transceiver chip is fabricated in a 0.13 ${\mu}$m CMOS technology. The die area of the radar IC occupies the area of 8.58 mm$^{2}$. In Fig. 9, the photos of the radar IC and the radar module are presented. The TWR radar IC can dramatically minimize the number of external components and reduces the size of the radar sensor module for the light weight TWR equipment. Fig. 10(b) shows the measured power spectrum of the impulse transmitter of UWB radar IC, where the center-frequency is 1.19 GHz with 600 MHz bandwidth at 10~MHz PRF (Pulse Repetition Frequency).

The time-domain waveform of the transmitted impulse is also shown in Fig. 10(a). The receiver RF front end part of the radar IC, which includes the LNA to the RF power splitter, is measured with the additional RF output port.

As shown in Fig. 11, the gain and noise figure of the receiver RF front end part are 35.3 dB and 3.2 dB at 1.2 GHz, respectively. To suppress the many commercial interferers around 900 MHz, a RF notch filter using L and C passives is realized at the RF receiver path on the test board, so that the gain curve abruptly goes down near the 900 MHz range. The current consumption of the full radar IC is 116.3 mA from 1.2 V supply.

To enhance the transmitter power and receiver sensitivity by the compensation of the through-wall loss, the final radar module as shown in Fig. 9 employs the external power amplifier and low noise amplifier, whose gains are about 20 dB and 15 dB, respectively. In the actual through-wall radar experiment, it is necessary to separate people behind the wall from the clutters and background noise because many environmental reflectors other than the human target are detected during the measurement. For this reason, the moving target indication (MTI) processing is useful for emphasizing the motion and discriminating the human target from the background clutters. Fig. 12 shows the measured and processed results of the detection for the people beyond the wall at the distance of 5.2 m and 9.4 m, respectively. By applying the simple MTI algorithm and extracting the signal envelope, a human can be detected up to 9.4 m beyond the two 24 cm-thick concrete brick wall. The final summary and comparison of the through wall radars are shown in Table 1.

Fig. 9. Photos of TWR radar IC and sensor module.
Fig. 10. Measured impulse waveform and power spectrum.
Fig. 11. Measured gain and NF of receiver RF front end.
Fig. 12. Measured waveform of through wall radar with signal processing.
Table 1. Comparison of UWB TWRs and UWB radar SoCs





Detection range

(wall type, human)


DC power

CMOS Tech.


3 / 9 GHz

(BW 1GHz)

Discrete Module


> 2 m

(drywall panel)

1.5 cm

(100 ps)




3 – 5 GHz

Commercial Module


~ 2.3 m

(concrete wall)

6.5 cm

(Time Domain P220)



3 - 5 GHz

Radar SoC


> 3.5 m

(concrete wall)

1.5 cm

115 mW


130 nm CMOS


0.8 – 5 GHz

(BW 2.5 GHz)

Radar SoC

Human feature


0.73 cm

695 mW


130 nm CMOS


6.6 – 8 GHz

Radar SoC


9 m

4.2 mm

118 mW


55 nm CMOS

This work

0.9 – 1.5 GHz

Radar SoC


> 9.4 m

(with PA, LNA)

3 cm

(200 ps)

139 mW


130 nm CMOS


A 0.9 – 1.5 GHz UWB radar IC and sensor module for the through-wall detection of human is presented in this paper. In order to enhance the SNR and resolution, the ETS and time-interleaved sampling technologies are used with the embedded timing circuit (DLL). The DC offset cancellation circuit using 8-bit DAC improves the dynamic range of the receiver while preventing from the analog output saturation. The through-wall radar demonstration with the help of digital signal processing is performed for the human behind the concrete brick wall, and the maximum tracking distance is up to 9.4 m.


The authors gratefully acknowledge the financial support provided by Defense Acquisition Program Administration and Defense Industry Technology Center under the contract UD160005D and also by the Research Grant of Kwangwoon University in 2022.


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Byeong Jae Seo

Byeong Jae Seo received the B.S., M.S. degrees in Electronics Engi-neering from Kwangwoon University, Korea, in 2017, 2019 respectively. Currently, he is working toward the Ph.D. degree at KwangWoon Univer-sity. His research interests include CMOS RF/analog IC design for wireless communication system and UWB radar transceivers.

Gu Jung

Gu Jung received the B.S. degree in electromagnetic-wave engineering from Kwangwoon University, Korea, in 2008. Since 2011, he joined Silicon R&D inc. as a CMOS RFIC desinger. His research interest includes CMOS RF/analog IC design for various radars and communication systems.

Sunghun Jung

Sunghun Jung received the B.S. degree in electronics engineering from Myongji University, Yongin, South Korea, and the M.S. degrees in electrical and electronic engineering from Yonsei University, Seoul, South Korea, in 2012. He is currently a research engineer with the EW R&D Center, LIG Nex1. His research interests include RF system and positioning systems.

Dong-Min Seol

Dong-Min Seol. received the B.S. degree in electronics engineering from Soongsil University in 2005. He received the M.S. and Ph.D. degrees in broadband network engineering from University of Science and Technology in 2011. He is currently a Research Engineer LIG Nex1. His research interests include indoor positioning, through-wall radar and wireless communications.

Sungmoon Chung

Sungmoon Chung. received the B.S., M.S. and Ph.D. degrees in electronic computer communication engi-neering from Hanyang University in 2012. He is currently a researcher engineer with the Defense Industry Technology Center, ADD(Agency for Defense Development). His research interests include 5G/6G, WSNs, SDN, Radar systems.

Yun Seong Eo

Yun Seong Eo received the B.S., M.S., and Ph. D degrees in Electrical Engineering all from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1993, 1995 and 2001, respectively. From 2000 to 2002, he had been with LG Electronics Institute of Technology, Seoul, Korea, where he was involved in designing RF integrated circuit (RFICs) such as VCO, LNA, and PA using InGaP HBT devices. In September 2002, he joined Samsung Advanced Institute of Technology, Yongin, Korea, where he developed 5-GHz CMOS PA and RF transceivers for 802.11n target, and was also involved in the development of 900 MHz RF identification (RFID) and 2.4-GHz ZigBee RF transceivers. In September 2005, he joined Kwangwoon University, Seoul, Korea, where he is currently a professor with Electronics Engineering department. Recently, he has developed so many RF transceiver ICs for the WPAN/WBAN and narrow band IoT devices. And he has been focusing on CMOS UWB and FMCW Radar ICs for surveillance system and proximity fusing. In 2009, he founded Silicon R&D Inc, where he is CEO and develops CMOS based UWB radar ICs and low power/low rate communication RFICs.