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  1. (Department of Electric Engineering, Gangneung-Wonju National University, Gangneung, 25457, Korea)

Synaptic device, ReRAM, SWCNT, AI semiconductor


Von Neumann architecture has low computation efficiency, resulting in high power consumption. In other words, when the core processing unit (CPU) transmits data to memory, bottlenecks occur, as the random access memory (RAM) cannot keep up with the computational speed of the processing units. Neuromorphic architecture, an artificial intelligence (AI) computing technology that requires a large amount of data to be calculated, has been proposed to solve this problem. Various studies have found memories with fast computing speed, non-volatility, and high integration. A memristor based on a neuron-synapse mechanism has been proposed as an example of a neuromorphic semiconductor implemented as a next-generation device. Many researchers have also actively studied spiking neural networks (SNNs), a type of artificial neural network (ANN). The human brain has 10$^{11}$ neurons and 10$^{15}$ synapses connected in parallel at a capacity of about 2 L. Learning and memory are simultaneously performed with a power of about 20W. Synapses play a role in transmitting spike signals generated from pre-neurons to post-neurons through chemical and electrical reactions. This mechanism is called spike-timing-dependent plasticity (STDP). STDP modifies the strength of connections in NNs. In other words, the process varies the synaptic weight based on the neurons’ pre- and post-spike relative timing. The synaptic device is divided into short-term and long-term with excitement and suppression. Therefore, a memristor-based on STDP may be expressed in various memory states other than 0,1.

Fig. 1. The proposed MOCS structure.


Resistive random access memory (RRAM), a RAM-based SNN, has a metal-oxide-metal (MOM) or metal-oxide-N$^{+}$Si (MOS) structure and two types of mechanisms: the valence change mechanism (VCM) and electrochemical metallization (ECM). The ECM induces cations to form filaments, whereas VCM has a conductive path in the anode and generates and recombines oxygen vacancies (V$_{\mathrm{o}}$) to regulate the resistance. The virgin state of VCM is an initial high-resistance state (HRS) state in which low concentrations of oxygen vacancies exist in oxide. Then, while a forming voltage is applied to the top electrode (TE), breakdown occurs in the oxide, generating V$_{\mathrm{o}}$ and forming filaments through which current flows between electrodes. This phenomenon is called electroforming, in which the electric field and temperature increase together, producing positive feedback that generates many oxygen vacancies at once, causing a rapid resistance change. Oxide-based RRAM can control resistance by repeating the set and reset processes after forming. If voltage is applied after forming, it again combines oxygen ions with the filaments to increase resistance (HRS), which is the reset process. The reset process has a more gradual resistance modulation than forming because after it, the filaments are broken, with oxygen vacancies breaking only around the interfacial layers. As a result, in the set process, which decreases the resistance to a low-resistance state (LRS), the filaments reconnect even lower than with forming voltage. To summarize, through adjustment of the applied voltage to the TE, the RRAM can achieve multiple discrete resistance states (HRS, LRS) and gradual resistance switching, representing the synaptic weight variation in NN models.

The RRAM can implement an ultra-dense crossbar array because it is feasible to implement the crossbar with only two access lines and 3D multilayer stacking. However, MOM has a higher sneak current than MOS does, and MOS operates at higher switching voltages than MOM does. Metal contact in the MOM structure has high conductivity because there is no bandgap, and metal-Si contact in the MOS structure creates a sufficient Schottky barrier to perform nonlinear current-voltage (I/V) switching.

The sneak current occurs between adjacent memory cells due to cross-talk interference in a synaptic array that comprises 1T1R (one transistor, one register). The sneak current leads to unnecessary energy consumption and reduces the reliability because it disturbs the precise resistance modulation with importing errors when programming/reading. Moreover, high switching voltages cause high energy consumption. It is thus necessary to retain RRAM’s advantages and solve its problems. Therefore, we propose the use of single-walled carbon nanotubes (SWCNTs) to fabricate a metal-oxide-SWCNTs-N$^{+}$Si (MOCS) synaptic device [3,4]. The MOCS is compatible with the complementary metal-oxide-semiconductor (CMOS) process and builds a Schottky barrier in semiconducting CNT- metal contact, inducing asymmetric IV curves [5]. Furthermore, the MOCS allowed the MOCS to become a self-integrated selector device. Therefore, the sneak current was reduced, and the density of the array increased because the selector layers were not needed.


Nanotechnology is currently in the spotlight as a potential solution to issues that have arisen while integrating devices in the memory industry. CNTs of 1D material are attracting attention as a new material due to their excellent stability and electrical properties. CNTs form a tube shape by rolling a graphite plate, and the diameter of the tube is only several nanometers. CNTs may be classified into SWCNTs or multi-walled carbon nanotubes (MWCNTs) according to the number of walls. SWCNTs have similar electrical properties to copper.

Moreover, SWCNTs have a high elastic modulus and strength. There is little change in the material, even after physical impact. Fig 2. shows their metallic and semiconducting characteristics depending on the chirality, structure, and the angle at which the graphite sheet rolls in terms of geometry [6]. Chirality refers to the torsional state of SWCNT molecules, which is explained by the chirality index (n,m).

In this study, SWCNTs with high electrical and physical properties were optimized for the electrode. SWCNTs have good metallic conductivity. In addition, they have a sufficient semiconducting band gap to practice a nonlinear I/V switching operation. Since the resistance is an appropriate value between Si and metal, the current flows through the formation of the electric field. The CMOS compatibility has the advantage of improving the integration of devices.

Fig. 2. The difference in chirality of SWCNTs [6].


Fig. 3 shows the process flow of the MOCS structure. In the fabrication, As dopant was completely doped on the p-type wafer substrate, as shown in Fig. 3(a). After the implantation process, annealing was performed at 1000 C$^{\circ}$ for 10 s using RTP equipment to promote the activation of As ions. The bottom electrode (BE) of N$^{+}$Si was then deposited on the substrate. Accordingly, an HfO$_{\mathrm{x}}$ layer thickness of 5 nm was accumulated on the BE using the atomic layer deposition (ALD) method. After mask patterning, the TE was formed on the HfO$_{\mathrm{x}}$ layer with a thickness of 100 ${\mu}$m by direct current sputtering. Then, SWCNT dip-coating flow was performed. SWCNT liquid is very watery, so it was diluted deionized water in a ratio of 1:3. Next, SWCNTs were released with ultrasonic equipment because they have Van der Waals force, which enables forces to become entangled with each other. The sample was then immersed in the SWCNT solution. As a result, SWCNTs were placed at 3~nm on N$^{+}$Si. Fig. 3(b) shows the Raman spectra of the as-deposited SWCNTs by CNT dip-coater. The G peak was centered around 1592 cm$^{-1}$. According to the restricted Boltzmann machine model of Raman spectra, SWCNTs were observed in inverse proportion to the diameter and frequency [7]. The CNTs’ G-band was divided into two functions: a G$^{+}$ peak and G$^{-}$ peak. Depending on the location of the G mode, if the (G$^{+}$peak > G$^{-}$ peak) condition was satisfied, the SWCNT material showed semiconducting abilities [8-10]. Fig. 3(d) shows CNT deposition, which had a diameter of 1.2-1.7 nm. As we intended, the G/D ratio of semiconducting CNTs was good, and the quality was excellent [7].

Fig. 3. (a) The fabrication flow of the Ti/HfO$_{\mathrm{x}}$/SWCNTs/N$^{+}$Si MOCS RRAM; (b) Raman spectroscopy of the SWCNTs, showing a distribution from 1200-1700 cm$^{-1}$. Five samples were measured; (c) Entanglement property of SWCNTs - Van der Waals force; (d) A scanning electron microscope image of typical SWCNTs.


Fig. 4(a) shows a schematic diagram of Ti/HfO$_{\mathrm{x}}$N$^{+}$Si of the MOS structure, in which the TE was Ti and the bottom electrode was N$^{+}$Si [11]. Fig. 4(b) shows the I/V switching behavior of an RRAM device with unipolar switching characteristics. The set and reset processes were both observed at the positive polarity voltage. During the initial positive bias, the set voltage was 6.55V, and a 500 ${\mu}$A compliance current was enforced to limit the current through the device. The mechanism of RRAM could thus be a set process from the HRS to the LRS. During the second positive bias, the reset voltage was 1.7 V. The RRAM resistance could thus be a reset process from the HRS to the LRS. Memory with unipolar switching operation can be set and reset with one polarity voltage, which makes it easy to design and ensures relatively low power consumption [12].

Fig. 5(a) shows a schematic diagram of the Ti/HfO$_{\mathrm{x}}$/ SWCNTsN$^{+}$Si of the MOCS structure, in which the TE was Ti and the BE was SWCNTs. Fig. 5(b) shows the I/V switching behavior of an RRAM device with unipolar switching characteristics. The set and reset processes were both observed at the positive polarity voltage. During the initial positive bias, the SET voltage was 3.9 V, and a 500 ${\mu}$A compliance current was enforced to limit the current through the device. The mechanism of RRAM could thus be a set process from the HRS to the LRS. During the second positive bias, the reset voltage was 1.1 V. The RRAM resistance could thus be a reset process from the HRS to the LRS. As a result of the implementation of MOCS RRAM, V$_{\mathrm{set}}$ decreased by 60%, and V$_{\mathrm{reset}}$ decreased by 70%. The semiconducting SWCNTs were optimized as the BE to perform low-voltage operation of the synapse. Finally, Table 1 summarizes the comparison of set & reset voltage and on/off ratio proven synaptic devices.

The performance of resistance change was altered to be consistent with a digital signal, whereas the gradual conduction state change with continuous conductance behaviors showed similar characteristics to a biological synapse [12]. Therefore, the fabricated RRAM devices were measured by Vacuum Probe Station and Semiconductor Parameter Analyzer (HP4156A). After the device forming voltage, Fig. 6(a) shows the potentiation behaviors by repeating the (0 ~ 2 V) voltage sweeps. On the other hand, Fig. 6(b) shows the depression behaviors by repeating the (0 ~ -2 V) voltage sweeps. As a result, it demonstrates that synaptic weight can be expressed in various memory states. Fig. 7(a) and (b) shows the gradual set and reset of the synaptic device and simulates the potentiation and depression performance after the application of a continuous pulse.

Table 1. Comparison of HfO$_{\mathrm{x}}$-based RRAM devices
Fig. 4. (a) Schematic drawing of the fabricated MOS RRAM; (b) Typical I/V characteristics of the MOS RRAM.
Fig. 5. (a) Schematic drawing of the fabricated MOCS RRAM; (b) Typical I/V characteristics of the MOCS RRAM.
Fig. 6. (a) Potentiation by repeating (0 ~ 2 V) voltage sweeps; (b) Depression by repeating (0 ~ -2V) voltage sweeps.
Fig. 7. (a) Synaptic gradual set modulation; (b) Synaptic gradual reset modulation.


In recent years, implementation of memristors using nano-based materials has attracted attention. And it is important to reduce the power consumption of memristors. To reduce the operation voltage of RRAM, new materials for the metal electrodes need to be developed. When the device area is reduced to the nano-meter size, the resistance switching devices may be synaptic properties with high density and low energy consumption reliability. In this study, SWCNTs were optimized for electrical, physical, and mechanical properties that are superior to Si at room temperature. Thus, the I/V curve induced by the Ti electrode of the synaptic devices were analyzed. The measurement results showed unipolar switching behavior and a gradual set and reset process. As a result, when the BE was compared with N$^{+}$Si and SWCNTs, the RRAM based on SWCNTs was operated at a lower voltage.


This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (2021R1G1A1093786). It was also supported by the 2022 Academic Research Support Program in Gangneung-Wonju National University.


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DongJun Jang

DongJun Jang received a B.S. degree in electronic engineering from Gangneung-Wonju University (GWNU, Korea) in 2022. Since 2022, he has now been working on M.S. course at GWNU. Currently, he is conducting optoelectronic synaptic device and chemresistive sensor research at the Intelligent Semiconductor Device & Circuit Design Laboratory (ISDL) according to Professor Min-Woo Kwon.

HyunWoo Ryu

HyunWoo Ryu has been studying in the Department of Electronic Engi-neering at Gangneung-Wonju Na-tional University (GWNU, Korea) in 2018. From 2021 to 2022, Resistive switching device (RRAM) and semiconductor TCAD simulation research were conducted with Professor Min-Woo Kwon. He is currently attending school.

HyeonJin Cha

HyeonJin Cha has been a Gangneung-Wonju National Univer-sity (GWNU, Korea) in electronic engineering since 2018. From 2021 to 2022, he researched resistance switching devices (RRAM) and semiconductor fabriccation. In 2022, He studies Sound Event Detection (SED) at the Laboratory for Machine Auditory Perception (L-MAP) with Professor Sangwook Park.

Na-Young Lee

Na-Young Lee has been a B.S. student of electronic engineering at Gangneung-Wonju National Univer-sity (GWNU, Korea) since 2019. From 2020 to 2022, she conducted research on semiconductor circuit design and fabrication optimization with Professor Min-Woo Kwon in the Intelligent Semiconductor Device & Circuit Design Laboratory (ISDL). She is now attending school.

Younglae Kim

Younglae Kim received his Ph.D. from Department of Electrical and Computer Engineering at North-eastern University (Boston, MA, USA) in 2013. After Ph. D., he worked at Intel Corporation (Hillsboro, OR, USA) as a PTD Engineer from 2013 to 2018. In 2018, he joined Gangneung-Wonju National University (GWNU, Korea) as a Professor, working in the Department of Electronic Engineering.

Min-Woo Kwon

Min-Woo Kwon was born in Inchon, south Korea in 1987. He received B.S. and Ph. D. degrees in depart-ment of Electrical and Computer Engineering from Seoul National University (SNU) in 2012 and 2019, respectively. From 2019 to 2021, he worked at the Samsung semiconductor Laboratories, where he contributed to the development of 1x nm DRAM cell transistor and its characterization. In 2021, he joined Gangneung-Wonju National University (GWNU, Korea) as an assistant professor in the Department of Electric Engineering, where he is currently a professor.