A 39.8% locking range injection-locked quadrature voltage-controlled oscillator (IL-QVCO) using fourth-order resonator is proposed. The fourth-order resonator is applied to widen the locking range compared with the conventional IL-QVCO using a second-order resonator. The self-oscillation frequency of the proposed IL-QVCO is 7.89 GHz, and the input frequency locking range is 7.08–10.56 GHz (39.8%) at an input power of 0 dBm. The in-phase and quadrature (I/Q) phase difference is 0.6° in their mean value while the standard deviation reaches 4.87°. The power consumption of the core is 42 mW from a 1-V supply voltage. The size of the IL-QVCO chip fabricated in a 65-nm complementary metal–oxide–semiconductor (CMOS) technology is 0.86 mm × 0.77 mm.

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## I. INTRODUCTION

In the wireless communication field, an in-phase and quadrature (I/Q) signal is used
for modulation methods such as quadrature phase shift keying and quadrature amplitude
modulation ^{(1,}^{2)}. In addition, it can be used to eliminate ghost targets in radar applications ^{(3,}^{4)}. The frequency band required by wireless communication and radar application is increasing
to the millimeter-wave band, and the bandwidth is also expanding. Therefore, a local
oscillator must be used to output the millimeter-wave I/Q signal with a wide frequency
range.

Fig. 1 shows four I/Q generator topologies: (a) frequency divider, (b) passive phase shifter,
(c) quadrature voltage-controlled oscillator (QVCO), and (d) injection-locked (IL)-QVCO.
The frequency divider receives the signal of f_{0} and outputs an I/Q signal, which decreases the frequency ^{(5,}^{6)}. Thus, it is not suitable for millimeter-wave frequency applications because a frequency
that is twice as high is necessary to generate the I/Q signal. In addition, an active
phase shifter, such as a polyphase filter (PPF), consists of passive components, including
resistors and capacitors, that consume no power ^{(7)}. The PPF is typically cascaded with different time constant to combat variations
in the process, voltage and temperature (PVT). In addition, calibration circuits and
driving amplifiers are used to calibrate the phase error and loss ^{(8)}. QVCOs can output a I/Q signal without an input signal; however, they have a considerably
narrow operation frequency range ^{(9-}^{11)}. The operation frequency ranges of a Colpitts QVCO ^{(9)} and a QVCO with tail current injection ^{(10)} are 0.217 GHz (4%) and 0.44 GHz (8%), respectively. The self-injection-coupled (SIC)-QVCO
^{(11)} and phase-tunable injection-coupled (PTIC)-QVCO ^{(12)} also have operation frequency ranges of 0.76 GHz (14%) and 0.6 GHz (6%), respectively.

Fig. 1. I/Q signal generator (a) frequency divider, (b) passive phase shifter, (c) QVCO, (d) IL-QVCO.

Table 1. Design parameters

## II. CIRCUIT DESCRIPTION

Fig. 2 shows a schematic of the proposed IL-QVCO that consists of an NMOS cross-coupled
pair (M_{1–4}, M_{9–12}), direct injector (M_{5, 6}), fourth-order resonator (L_{1, 2}, L_{5, 6}, C_{1–4}), and output buffer (M_{7, 8}, M_{13, 14}, L_{3, 4}, L_{7, 8}). The differential input signal (V_{in}^{+}, V_{in}^{–}) is applied to the gate of the injector (M_{5, 6}) through DC blocking capacitors (Cdc). The DC voltage (Vin,DC) is biased through
the high-impedance resistor (R_{dc}). The two nodes of the primary coil (L_{1}, L_{3}) are connected to the feedback injector (M_{3, 4}, M_{9, 10}); they oscillate with a phase difference of 90°. Additionally, in the figure, k represents
the coupling coefficient between the primary and secondary coils. The value of k determines
the self-resonance point. The I/Q signals (V_{out}^{I+}, V_{out}^{I–}, V_{out}^{Q+}, and V_{out}^{Q–}) are output from the secondary coil (L_{2}, L_{6}) nodes through the output buffer and have the same frequency as the input signals.
In other words, this IL-QVCO is injection-locked to the fundamental signal. The topology
of the output buffer is a differential common-source amplifier. The load impedance
of the output buffer is matched at 8 GHz. V_{bias} is generated by an internal self-bias circuit, which is not shown in the figure to
reduce complexity. The design parameters are organized in Table 1.

Fig. 3 shows the load impedance magnitude of the IL-QVCO with a second-order resonator and fourth-order resonator, as well as a half core schematic. The second-order resonator consists of L

_{1}and C

_{1}. Parasitic capacitors, including the drain–gate capacitors of M

_{1}–M

_{6}, are included in C

_{1}. This resonator has only one pole. The resonance angular frequency can be expressed as

The magnitude of the load impedance at w0 is the highest; however, the angular frequency range satisfied the oscillation condition is narrower than that of the fourth-order resonator

^{(13,}

^{14)}. The fourth-order resonator comprises two poles. If the design parameter satisfies the following formula,

then the resonance angular frequency can be expressed as

where k is the coupling coefficient between L

_{1}and L

_{2}. If the transformer is coupled strongly, the distance between the two poles increases, indicating that the locking range can be controlled by the coupling coefficient

^{(15,}

^{16)}. Fig. 4 shows the simulation results of the impedance magnitude according to the coupling factor, k

_{12}. As the value of k

_{12}increases, the distance between the two poles increases. Also, the self-resonant frequency is determined by the one with the higher impedance among the two poles. A wider operation frequency range can be obtained when a fourth-order resonator is used, rather than a second-order resonator, by adjusting the coupling coefficient. However, the locking range cannot be extended indefinitely because the IL-QVCO must satisfy the oscillation condition. The minimum oscillation condition follows the Barkhausen formula.

where g

_{m}is the transconductance of the NMOS cross-coupled pair, and ZL is the magnitude of the load impedance of the IL-QVCO. As the distance between the two poles increases, a new minimum value is obtained. The IL-QVCO should be designed using this minimum value to satisfy the oscillation condition.

## III. MEASUREMENT RESULTS

This circuit was implemented by using a 65-nm complementary metal–oxide–semiconductor (CMOS) technology. Fig. 5 shows a photograph of the die. The chip size is 580 mm × 600 mm, and the entire die size, including all pads, is 860 × 770 mm. The power consumption of the core and output buffer are 42 and 11 mW, respectively. Fig. 6 shows the simulated and measured locking range of the IL-QVCO when Vdc is 0.7 V, with a supply voltage of 1 V. The simulated and measured locking ranges are 7.6–10.3 GHz and 7.08–10.56 GHz, respectively, when a 0 dBm input signal power is applied. The measurement result of the locking range is very similar to the simulation result. The self-resonance frequency difference between simulation and measurement is only 0.23 GHz.

Fig. 7 presents the Monte Carlo simulation results of the I/Q output signal when an 8 GHz injection signal is applied. The number of samples is 10000, mean phase difference is 0.643. The standard deviation is 4.87. Fig. 8 shows the measured I/Q output power and the amplitude imbalance according to the injection frequency. The maximum I/Q amplitude error is less than 2-dB.

Fig. 8. Measured I/Q output signal power and I/Q amplitude mismatch according to the injection frequency.

Fig. 9 and 10 show the spectra when the minimum and maximum injection-locked frequencies are applied, respectively. The cables, connectors, and baluns used during the measurement produced an approximately 4-dB loss. Fig. 11 illustrates the phase noises for the cases when the 8 GHz injection-locked frequency is applied, and no input signal is applied. The self-oscillation frequency is 7.89 GHz, and the phase noise is −105.41 dBc/Hz.

Fig. 11. Measured I/Q output signal power and I/Q amplitude imbalance according to the injection frequency.

Table 2. Performance comparison of other injection-locked circuits for generating quadrature signals

*: single side lock range > 350 MHz

**: full chip size

^{(17,}

^{18)}. The phase noise in Table 2 is the value at each output frequency. The proposed IL-QVCO has the widest operation frequency range.

## IV. CONCLUSIONS

An IL-QVCO using a fourth-order resonator is implemented in a 65-nm CMOS technology. The fourth-order resonator is employed to generate wide frequency range of I/Q signals. The free-running frequency of the IL-QVCO is 7.89 GHz, and the input locking range is 7.08–10.56 GHz (39.8%) at an input power of 0 dBm. The I/Q phase difference is 0.6° in their mean value while the standard deviation reaches 4.87°. The phase noise is −124.92 dBc/Hz at an offset frequency of 1 MHz. The core power consumption was 42 mW from a supply voltage of 1 V. The die size was 0.86 mm × 0.77 mm.

### ACKNOWLEDGMENTS

This work was supported by Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government(MSIT) (No. 2018-0-01663, Development of Communication-Sensing Converged B5G Millimeter Wave System) and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2020R1F1A1074076).

### REFERENCES

## Author

Kwang-Il Oh was born in Gwang-myeong, Republic of Korea, in 1993.

He received his B.S. degree in physics and M.S. degree in electrical and electronics engineering from Chung-Ang University, Seoul, Re-public of Korea, in 2018 and 2020, respectively.

He is currently working toward his Ph.D. degree at the School of Electrical Engineering at Chung-Ang University.

His current research interests include CMOS RF transceivers for wireless communication and millimeter-wave radar.

Donghyun Baek (S’98–M’07–SM’13) received his B.S., M.S., and Ph.D. degrees in the department of electrical engineering, Korea Ad-vanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1996, 1998, and 2003, respectively.

From 2003 to 2007, he was with the System LSI Division of Samsung Electronics Company, Ki-heung, Korea, where he designed mobile broadcasting RF receivers, such as DVB-H, TDMB, and ISTB-T, and led the CMOS power amplifier project for handsets.

In 2007, he joined the School of Electrical Engineering, Chung-Ang University, Seoul, Korea, where he is currently an associate professor.

He is a life member of the IEEK and a senior member of the IEEE.

His research interests include analog, RF, and mixed-mode circuit designs for the mobile system on a chip(SOC), radar on a chip (ROC), and sensor on a chip (SOC).