KoBaekseok1
MinYoung-Jae2
-
(Visual Display Division, Samsung Electronics, Suwon, Gyeonggi-do 16677, Korea)
-
(Department of Electric and Electronic Engineering, Halla University, Wonju, Gangwon-do
26404, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Chip power model, power distribution network, current profile slope, power integrity, display timing controller
I. INTRODUCTION
With increasing functional and performance demands on electronic devices, power noise
management has been one of the most critical issue in the development process. In
particular, the consumer electronic devices seriously require robust power noise quality
in terms of system-level power integrity (1-3). In order to improve the power noise quality in the entire system, the complex power
integrity issues arising from integrated circuit (IC) design, package paths, printed
circuit board (PCB) environments and software operation, should be considered. Since
power noise considerations in the IC design stage is typically performed during or
after the physical implementation of the placement and routing (P&R), the improvement
of the system power noise quality by adjustment of factors associated with off-chip
power integrity can be a challengeable task.
For system level power noise problems, many efforts on the early phase of development
process have been conducted (4-19). However, since the previous methodologies of (4-12) require the IC layout information of the physical implementation, power noise management
in concurrent system design is not appropriate in terms of the development turnaround
time. In addition, the power noise estimation during the design stage of off-chip
design (13-19) is a backward solution that does not optimize the power noise at the IC level.
In order to estimate the power noise of the system on chip (SoC) from the perspective
of the system designer, our previous research of (20) developed a novel simplified chip power model (SCPM). The SCPM, which models of the
current profile with local blocks and clocks, enables the overall power noise estimation
with the power delivery network (PDN) in the early design stage before SoC physical
implementation without the silicon netlist or geometry layout information. However,
when applying the collective ratio between the current peak and base current, some
specified blocks do not match the power noise spectrum estimation. Due to adoption
of the simplified and generalized current profile, the developed methodology can exhibit
the low power noise estimation accuracy for specified applications such as display
timing controllers (TCONs). In this paper, an enhanced SCPM methodology for TCONs
is presented.
Fig. 1. Proposed PDN design process using SCPM methodology in (20) vs. conventional design process.
Section II reviews our previous SCPM methodology and demonstrates an enhanced SCPM
methodology for display TCONs. Section III and IV provide the verification results
and conclusions.
II. SCPM METHODOLOGY FOR DISPLAY TIMING CONTROLLERS
This section briefly reviews our previously proposed PDN design process using the
SCPM methodology in (20). Subsequently, an enhanced SCPM methodology, which includes the current profile slope
information for display TCONs, is proposed.
1. Review of Previous PDN Design Process
Fig. 1 shows our previous PDN design processes, excluding the design verification process.
Compared to the conventional board design process, our design process exploits our
novel SCPM methodology, that the SCPM is generated with the register-transfer-level
(RTL) information without using silicon physical implementation information. Since
the conventional design process is forced to be performed sequentially within the
limited development period, there is an irreversible risk to improve the system power
noise performance. Nevertheless, our power noise estimation using the SCPM methodology
helps reduce failures caused by power integrity performance issues prior to final
system design. In addition, the improved system power noise quality can be expected
due to the extended package and PCB development period.
Our previously proposed SCPM methodology has been validated using a digital TV (DTV)
system that included instant combinations of unit SCPMs according to various IC operation
scenarios. The SCPM methodology focuses the power noise estimation of the complicated
system operation incorporating the PDN with unit SCPMs during the early design stage.
2. Improved SCPM Methodology
As the test vehicle in this paper, the TCON, which is the main control IC of the display
panel, processes the input image data and transfers the output parallel buffered signal
towards the panel display driver ICs (DDIs). Since the power consumption associated
with the transmission of many parallel signals to DDIs increases according to the
demand for high resolution and frame rate, many studies on interfaces such as V-by-One
and the advanced intra panel interface (AiPi) including the traditional low voltage
differential signaling (LVDS) have been conducted (21,22). This section introduces an enhanced SCPM generation to improve the power noise estimation
accuracy for the display system using the LVDS interface between the TCON and DDIs.
The current profile of the unit SCPM in (20) is specified by a triangular shape with a transition time equal to 20% of the clock
cycle and a static current value [6, 8, 23, 24]. Considering that dominant power consumption
of the DTV processor SoC is mainly due to the operation of static CMOS logic circuits,
all SCPMs are generated using only one triangular piecewise linear (PWL) function.
However, in the case of special featured ICs such as the TCONs, the unit SCPM generation
with one simplified and generalized current shaped profile can degrade the power noise
estimation accuracy. In order to increase the estimation accuracy, the SCPM of the
first-in-first-out (FIFO) LVDS interface requires more detailed information.
Fig. 2(a) shows the typical output driver circuit of the conventional LVDS transmitter including
a nominal 100-Ω termination resistor RT in the receiver and parasitics in the package
and PCB. To transmit the differential signal, the output driver is configured as a
switched-polarity current generator with four MOS switches M1-M4 in a bridge configuration
and two voltage-controlled current sources MU, MD. The LVDS output voltage swing is
determined by the driver output current and termination resistance (Vsw,out = Isrc
∙ RT). Fig. 2(b) shows the simulated waveform of the driver consumed current excluding the DC bias
current with a fixed 100-Ω termination resistor and various LVDS voltage swings. Due
to the non-ideal operation of the two voltage controlled current sources, the LVDS
driver has an inconstant current flow during transition. Since the peak current transition
varies with the LVDS voltage swing, while the current transition interval remains
the same, the current profile slope is different. The TCON chip in this work uses
the LVDS voltage swing tuning option for optimal product quality. Fig. 2(c) shows the fast Fourier transform (FFT) spectrum of the PWL function with various
transition time to period ratios. Compared to the triangular current shape with a
transition time of 20% of the clock cycle in our previous work (20), the power noise estimation accuracy error of the spectral peak value under the same
consumed current amplitude can be up to 45%.
Fig. 2. (a) Conventional LVDS output driver circuit, (b) Simulated waveform of the
driver consumed current without DC bias current, (c) PWL function spectrum of the
simulated current waveform.
Fig. 3. Proposed SCPM generation and PDN implementation including the current profile
slope information.
In order to reduce the power noise estimation accuracy error induced by missing the
major system current slope information, which is the LVDS driver current slope information
in the TCON system, this work proposes a PDN using the enhanced SCPM methodology including
the current profile slope information as shown in
Fig. 3. The SCPM generation for the simulated power noise estimation includes PWL functions
with the LVDS driver current slope information. In this work, the PWL function for
the LVDS drivers comprises a transition time of 10% of the clock cycle, while the
other PWL functions comprise the transition time of 20%.
Table 1. Current consumption of each TCON block
|
Block
|
Current Consumption
|
Operating Frequency
|
|
#1
|
336 mA
|
280 MHz
|
|
#2
|
762 mA
|
280 MHz
|
|
#3
|
469 mA
|
150/300 MHz
|
|
#4
|
65 mA
|
300 MHz
|
|
#5
|
410 mA
|
300 MHz
|
|
#6
|
1599 mA
|
300 MHz
|
|
#7
|
1109 mA
|
300 MHz
|
|
#8
|
727 mA
|
933 MHz
|
|
#9
|
48 mA
|
300 MHz
|
|
#10
|
1091 mA
|
300 MHz
|
III. VERIFICATION AND MEASUREMENT RESULTS
We experimentally verified the proposed SCPM methodology with a PDN including the
TCON chip, package, and PCB. The PDN for TCON power noise estimation consists of on-chip
components (on-die resistor and capacitor), off-chip components (off-chip decoupling
capacitors and inductor), and PWL current sources with the current slope information
including the external voltage regulator module (VRM) on the PCB as shown in Fig. 3. While the on-chip components are experimentally extracted, the off-chip components
are extracted in S-parameter form on the basis of EM simulation. The extracted on-die
resistance ROD and capacitance COD values are 2.5 mΩ and 105 nF, respectively. And
the package capacitors have 23 mΩ of equivalent series resistance and 1.2 nH of equivalent
series inductance. The test vehicle of the display TCON is synchronized with a 300
MHz reference clock and the other peripheral blocks are 933 MHz for the memory controller,
while the raw image data receiver block uses a 280 MHz clock. Table 1 shows the current consumption and operating frequency of each TCON block. Unlike
the SoC chip in the previous work of (20), each sub-block in the TCON chip of this work operates simultaneously.
The current shape based on the enhanced SCPM methodology with the current profile
slope information is modeled as a triangular profile with the accumulated operating
TCON blocks. With the exception of the SCPM generation of the LVDS output buffer,
all SCPM have a triangular current shape with a transition time of 20% of the clock
cycle. Using the current consumption and operating frequency information, the current
shapes of each block in the test vehicle are defined according to a 4:1 current peak:
static current ratio. Additionally, each is correlated with the current peak and static
current after the current transients have been calibrated in the frequency domain.
The total current consumption is estimated as 6.48 A based on the root-mean-square
(RMS) at the RTL level. As shown in Fig. 4, the estimated transient peak-to-peak noise voltage is 66 mV and 7.18 mV of 300 MHz
in the frequency domain.
Fig. 4. Simulated result of the transient power noise estimation under the worst-case
current consumption condition including the 30 mV voltage drop of the power regulator.
Fig. 5. Top view of the TCON evaluation board.
Fig. 5 shows the evaluation board with the DTV TCON chip for the experimental verification.
The test vehicle is assessed in terms of voltage noise while the system runs 3D test
movies. To verify the voltage noise simulation results, the bottom point of the thru-via
on the center of the power ball allocation is taken as the test point.
Fig. 6. shows the measurement results of the power noise in each time domain and frequency
domain. Long-term fluctuations of less than 100 MHz caused by the DC–DC converter
output constant are ignored. The measured peak-to-peak power noise is up to 80 mV,
and is 6.75 mV at 300 MHz in the frequency domain. The main spectrums are 300 MHz
and its harmonics.
Fig. 7 compares the main spectrum distribution between the simulated and measured power
noise values. Compared to our previous work
(20), the proposed enhanced SCPM methodology is measured and confirmed that the frequency-domain
peak harmonic voltage is improved by 28%, while the time-domain peak-to-peak voltage
is improved by 6%. The standard deviation of the frequency-domain comparison in this
work is 0.514, while that in
(20) is 0.867. The harmonic amplitude between the simulated and measured data has the
same tendency. In the 150 MHz power noise spectrum, there is a large error between
the measurement and estimation, which is due to the 150 MHz external power noise coupling
in the entire TCON system.
Fig. 6. Measurement results on the 3D DTV operation.
Fig. 7. Power noise spectrum comparison between the estimation and measurement.
IV. CONCLUSIONS
This paper proposes an enhanced SCPM methodology including the current slope profile
information for the TCON of DTV applications. As we conclude from this experience,
the proposed SCPM methodology can be applied to predict the harmonic profile of the
current consumption, and is able to refine the peak amplitude of the current shape.
The risk of error in the voltage noise estimation carried out during the early stage
of the design process is verified using a display TCON operated with the FIFO approach.
ACKNOWLEDGMENTS
This work was supported by the NRF (2019R1F1A1061539). And the EDA tool was supported
by the IC Design Education Center (IDEC), Korea.
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Author
Baekseok Ko received the B.S. and M.S. degrees from Dongguk Univer-sity, Seoul, South
Korea, in 2003 and 2005, and the Ph.D. degree from Korea University, Seoul, Korea,
in 2016.
He joined as research professor at the center of semiconductor technology in Korea
University from 2017 to 2018.
He was with the UMTS RF Laboratory, Flextronics Mobile, Korea, from 2005 to 2008.
Since 2008, he has been with the Visual Display division of Samsung Electronics, Suwon,
Korea.
His current research interests include signal integrity, power integrity, and transceiver
design for high-speed interfaces.
Young-Jae Min received the B.S., M.S., and Ph.D. degrees in electrical engineering
from Korea University, Seoul, Korea, in 2006, 2008, and 2011, respectively.
In 2012, he joined the Memory Division of Samsung Electronics Corporation, Hwasung,
Korea.
In 2016, he founded SENTOUS Co., Ltd., Seoul, Korea.
Currently, he is an assistant professor with the Department of Electric and Electronic
Engineering at Halla University.
His research interests focus on high-speed CMOS transceiver and mixed-signal integrated
circuits, including sigma-delta data converters and Nyquist-rate data converters.