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  1. (Department of Electronic Engineering, Gachon University, Seongnam-si, Gyeonggi-do 13120, Korea )
  2. (Hewlett Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA, 95035, USA )
  3. (Electronics and Telecommunication Research Institute (ETRI), Yuseong-gu, Daejeon 34129, Korea )
  4. (Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea )

Photodetector, silicon-on-insulator, germanium-on-silicon, back-end-of-the-line, optical responsivity, metallization scheme


Photodetectors are a core component of integrated optoelectronic circuits and have been widely studied (1-4). Si photonics has been consistently finding a way out to chip-level production for future CMOS interconnection technology (5). Ge is gaining increasing popularity as an optical material in Si photonics owing to its genuine energy-band structure warranting higher probability of optical processes and relatively high Si compatibility (6). More recently, hexagonal atomic arrangements of Si and Ge in the low dimensions have been highlighted owing to its greatly increased change for transition to a direct-bandgap material and bandgap tunability (7). In this study, a Si waveguide-coupled 1,550-nm Ge-on-Si photodetector on silicon-on-insulator (SOI) is fabricated and contact engineering is carried out in the back-and-of-the-line (BEOL) for improving its direct-current (DC) performance. The fundamental reason for bringing 1,550-nm wavelength into the Si photonics is its local minimum in optical attenuation in the silica, or SiO$_{2}$, which is a very accessible material in the conventional Si processing, with is potential applicability in the low-loss optical waveguide (8-10). By introducing a single-layer scheme comprising in-plane contacts with Metal-1 and a double-layer scheme comprising contacts with Metal-1 and extended Metal-2, the responsivity has been prominently improved.


SOI is etched for defining the device active region first, in the mesa isolation for electrical isolation, and then, p$^{+}$ ion implantation is performed for forming the anode junctions. Ge is epitaxially grown with a thickness of 500 nm for a pseudomorphic growth on SOI and etched down to the Si region. n$^{+}$ ion implantation is performed forming the cathode junctions on Ge. The low-doping region of the Si where the high p-type doping has been screened is remained as the intrinsic region, by which Ge-on-Si p-i-n diode structure is constructed (11). After annealing the implanted dopants, inter-layer dielectric (ILD) deposition and the first metallization (Metal-1) are performed. Then, inter-metal dielectric (IMD) deposition and the second metallization (Metal-2) are performed. A passivation oxide is deposited and opened for contact pad, and the process is completed by alloying the wafer. Fig. 1 shows the cross-section of a fabricated device in which buried oxide (BOX), SOI, and epitaxially grown Ge active layer are clearly demonstrated.

Fig. 1. TEM image of the cross-section of a fabricated device.


Fig. 2(a) and (b) show the full and magnified views of the waveguide-coupled Ge-on-Si photodetector with bulk-metal contact (BMC) scheme by scanning electron microscopy (SEM), respectively. The length and width of the Ge active region are 96 μm and 8 μm, respectively, and the lateral distance between n$^{+}$ Ge and p$^{+}$ Si is 4 μm. The numbers of vias through which the anode and cathode are contacted by Metal-1 are 42 (21 on each side) and 17, respectively, in the single-layer contact (SLC) scheme, as shown in Fig. 2(c). The numbers of vias from Metal-1 to Si and Ge active regions are 22 (11 on each side) and 9, respectively, and those from Metal-2 to Metal-1 are 20 (10 on each side) and 8 in the double-layer contact (DLC) scheme, as shown in Fig. 2(d). Fig. 3(a) and (b) show the schematics of the SLC and DLC, respectively. These interconnection types can be more tangibly understood if seen from the sides as shown in the figures. It is demonstrated that the number of vias on the anode and cathode electrodes observed from top is maintained for SLC and DLC devices by this approach in the layout design. For the comparison study, BMC acts as the reference. In the BMC scheme, Metal-1 is directly deposited on Ge without contact holes: same with the SLC scheme in Fig. 3(a) but Metal-1 is volume-contacted to Ge without Via-1, which can be also confirmed by Fig. 2(b).

Fig. 2. SEM images of the fabricated devices (a) Top view of the entire Si waveguide-coupled Ge-on-Si photodetector. Magnified views of devices with (b) BMC (reference), (c) SLC, (d) DLC metallization schemes.



Fig. 3. Schematics seen from the sides for understanding the metallization schemes (a) SLC, (b) BLC interconnections.



The devices are mounted onto a temperature controlled copper stage held at 25 $^{\circ}$C. 1550-nm light is edge coupled into the photodetector waveguide through the use of a polarization maintaining (PM) lensed fiber. Polarization control is performed with the use of a polarization controller and polarizer at the input side and measurements were performed for TE polarization. For the DC characterization of each device, the dark current and responsivity are evaluated under various bias conditions. The cathode voltage (V$_{\mathrm{C}}$) is swept from 0 V to 4 V, while the anode pads on both sides of the Ge cathode are grounded in common (V$_{\mathrm{A}}$ = 0 V) for measuring the cathode current (I$_{\mathrm{C}}$) with no optical input. Fig. 4(a) shows the I$_{\mathrm{C}}$-V$_{\mathrm{C}}$ curves for the devices with BMC, SLC, and DLC schemes. Fig. 4(b) is a reproduction of Fig. 4(a) in terms of I$_{\mathrm{C}}$ values at several discrete V$_{\mathrm{C}}$ values, which allows more explicit comparisons to be made among the devices. It is revealed that the SLC and DLC schemes are substantially effective in reducing the reverse current, and the latter exhibits the minimum dark current. For the devices under measurements, the dark current is mainly composed of leakages from the Ge/Si heterojunction and metal-semiconductor (MS) interfaces. The heterojunction leakage is predetermined by the process and device dimensions, which are identically designed for all the devices, and therefore, the effectiveness of the interconnect SLC and DLC schemes is in the controllability of the MS interface leakages. The total contact area of BMC device where the metal is volume-contacted with the semiconductors is reduced by introducing segmented contact holes in the other schemes. The MS leakage is mainly governed by the contact area (12-14), and the total dark current is consequently reduced by the scaled MS interface leakages. A further reduction in the dark current is observed when the scheme transitions from SLC to DLC because the number of contacts between Metal-1 and the active regions through Via-1 is reduced by half.

Fig. 4. Dark current characteristics (a) IC-VC curves under reverse bias, (b) Comparison of dark currents among devices at different operating voltages.


Fig. 5. Evaluation of responsivity (a) Measurement setup verification by a BMC device (V$_{\mathrm{A}}$ swept with V$_{\mathrm{C}}$ = 0 V), (b) I$_{\mathrm{C}}$-V$_{\mathrm{C}}$-curves from the devices with different metallization schemes (V$_{\mathrm{A}}$ = 0 V), (c) Extracted responsivity values.


A wavelength of 1550 nm is widely used for an optical telecommunication channel owing to the lowest attenuation loss in the silica fiber and is being pursued for processing signal in on-chip optical interconnect (15). The final input power from a 1550-nm laser source is -0.5 dBm (0.89 mW). Fig. 5(a) shows the electrical response of the Ge-on-Si photodetector (BMC) to the 1550-nm optical input, by which the electrical and optical measurement setups are validated. As the interconnect scheme transitions from SLC to DLC, the collected photocurrent increases, as depicted in Fig. 5(b). Although the responsivity of each device is improved under a larger reverse bias, the DLC device exhibits the highest responsivity among the devices under all bias conditions, as can be confirmed from Fig. 5(c). Increased number of contacts in a given area (SLC) and a shorter path from the active regions to the elongated Metal-2 (DLC) improve the responsivity by avoiding current localization and enhancing the efficiency of photocurrent collection (16).


A waveguide-coupled 1550-nm Ge-on-Si photodetector is designed, fabricated, and characterized with a particular interest in the BEOL technology for improved performance. It is observed that an increased number of smaller contacts on the active regions and higher accessibility to the metal pad warrant substantial reduction in the dark current and enhancement in the responsivity.


This work was supported by the National Research Foundation of Korea (NRF) funded by the Korean Ministry of Science and ICT (MSIT) through a Mid-Career Researcher Program (NRF-2017R1A2B2011570) and by the Ministry of Trade, Industry and Energy (MOTIE) through the Korea Semiconductor Research Consortium (KSRC) Support Program (Grant 10052928).


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Seongjae Cho

Seongjae Cho received the B.S. and the Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2004 and 2010, respectively.

He worked as an Exchange Researcher at the National Institute of Advanced Industrial Science and Technology (AIST) in Tsukuba, Japan, in 2009.

He worked as a Postdotoral Researcher at Seoul National University in 2010 and at Stanford University, CA, USA, from 2010 to 2013.

Currently, he is working as an Associate Professor at the Department of Electronic Engineering, Gachon University, Korea.

His research interests include nanoscale CMOS devices, emerging memory technologies, group-IV optical devices, and hardware-driven intelligent devices and systems.

He is a Life Membeer of the IEIE.

Stanley S. Cheung

Stanley S. Cheung received the B.S., M.S., and Ph.D. degree in electrical engineering from the University of Southern California, Columbia University, and the University of California, Davis respectively.

He currently works as a Senior Research Scientist at Hewlett-Packard Laboratories in Palo Alto, CA., USA, and is engaged in high-bandwidth photonic device development for optical interconnects.

His previous work includes hybrid III-V/Si lasers/SOAs, III-V mode-locked semiconductor lasers, III-V widely tunable lasers, and silicon photonic integrated circuits.

Yung Hun Jung

Yung Hun Jung received the B.S. and M.S. degrees in electronic engineering from Gachon University, Korea, in 2018 and 2020, respec-tively.

His research interests include design of nanoscale CMOS devices, development of semiconductor processing, and optimal design of passive optical devices such as photodetector and distributed Bragg reflector.

Sae-Kyoung Kang

Sae-Kyoung Kang received his Ph.D. degree in electrical engi-neering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea, in 2006.

In 2006, he joined ETRI, where he is currently working on high-speed optic module and 2.5D/3D optical-electrical integration.

Dal Ho Lee

Dal Ho Lee received the B.S., M.S., and the Ph.D. degrees in control and instrumentation engi-neering from Seoul National University, Seoul, Korea, in 1982, 1985, and 1992, respectively.

He worked as an Exchange Researcher at University of Sourthern California, CA, USA, from 1997 to 1998.

Currently, he is working as a Professor at the Department of Electronics Engineering, Gachon University, Korea.

His research interests include smart city, IoT sensors, ultra-fast system interconnection, information and telecommunication facilities, and navigation.

Byung-Gook Park

Byung-Gook Park received the B.S. and the M.S. degrees in electronic engineering from Seoul National University in 1982 and 1984, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1990.

From 1990 to 1993, he was with AT&T Bell Laboratories, where he contributed to the development of 0.1-μm CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, developing 0.25-μm CMOS.

In 1994, he joined Seoul National University. He led the Inter-university Semiconductor Research Center (ISRC), Seoul National University, as the Director from 2008 to 2010.

He received Best Teacher Award from Seoul National University in 1997, Education Award from College of Engineering, Seoul National University in 2006, Haedong Academic Research Award from IEIE in 2008, the Minister Award for Nano Research Innovation from the Korean Ministry of Science, ICT and Future Planning in 2013.

He is an IEIE Life Member, Member of the National Academy of Engineering of Korea, and IEEE Fellow.