I. INTRODUCTION

Recently, the demand for a low power and high resolution ADC (Analog to Digital Converter) has been increasing with the development of bio-signal processing system. A single block that consumes most of power in DSM (Delta Sigma Modulator) is OPAMP(Operational Amplifier). The design methodology to decrease power consumption of the conventional DSMs is either to reduce the number of OPAMPs or to replace OPAMPs with other circuits which consumes less power within DSM. The conventional 4^th-order DSM usually requires four OPAMPs. The first methodology to design 4^th-order DSM^[1] for low power consumption was to employ two amplifiers with time-interleaving technique. However, this method suffers from one disadvantage. In other words, this conventional delta-sigma modulator tends to increase the input capacitor, reduce kT/C noise, and decrease back-end capacitor to reduce the layout area^[2]. Therefore employment of the same amplifier at the front and back-end stage of DSM becomes less efficient in terms of capacitances, power consumption, and layout area. The second technique is to design a delta-sigma modulator based upon utilizing inverters instead of operational amplifiers^[3,4]. This method allows inverters operating in the weak inversion region to be able to utilize a low power supply voltage and consequently, low power consumption. This technique suffers from finite gain of the inverter. The third design methodology practiced in the literature is involved with time-interleaving technique and digital signal processing technique^[5]. In the circuit proposed in [5]^[5], the first-stage integrator and the second-stage integrator are implemented with the single operational amplifier and the time-interleaving method, and the third-stage integrator is implemented by digital signal processing. However, the 5-bit flash ADC employed as a quantizer for digital signal processing resulted in a large power consumption.

In this paper, a CMOS 4^th-order DSM with a single reconfigurable fully differential operational amplifier is described. In order to reduce the power consumption of the proposed DSM, a design technique to reuse the single reconfigurable fully differential operational amplifier four times is employed by the four individual integrator stages within the proposed DSM. The single reconfigurable fully differential OPAMP is converted into the two stage OPAMP with one compensation capacitor associated with a reasonable phase margin to guarantee stability in the first and second integrator stage of the DSM. The third and fourth integrator stages utilize the folded-cascode OPAMP reconfigured from the single reconfigurable OPAMP. It is reconfigured so that it is able to obtain acceptable phase margin and sustain stability of the DSM.

This paper is organized as follows. In section II, the design technique of the fourth order modulator with the single reconfigurable fully differential OPAMP is presented. The measurement results and performance comparison with other conventional works are discussed in section III. Conclusions are drawn in section IV.

II. THE PROPOSED ARCHITECTURE

The block diagram of the proposed architecture with the four different clock phases is presented in Fig. 1. The conventional fourth order DSM can be represented by the top block diagram shown in Fig. 1. It can be replaced by the proposed one with the four different clock phases, as shown in Fig. 1. During the first clock phase(Phase 1), the modulator samples and integrates the analog input signal. The second clock phase (Phase 2) allows the modulator to sample and integrate the output signal of the OPAMP generated from the first clock phase. The third clock phase(Phase 3) enables the modulator to accomplish the sample mode and integration mode operations on the output signal of the OPAMP from the second clock phase. During the fourth clock phase(Phase 4), the modulator samples and integrates the output signal of the OPAMP produced from the third clock phase. The operation of the proposed DSM explained above can be described by the noise transfer function (NTF), which are calculated by 'The Delta-Sigma Toolbox' using Matlab^[2].

NTF is given by (1) with coefficients in (2)–(5).

where coefficients, $C_{0}$, $C_{1}$, $C_{2}$, and $C_{3}$ within the NTF are extracted from the matlab simulation and these optimized coefficients of loop factors with stability issues considered are presented in Table 2.

The proposed methodology requires the DSM to operate at four times faster clock frequency than that of the conventional DSM due to four clock phases. In order for the proposed DSM to maintain the same OSR as the conventional ones, four times faster clock frequency than that of the conventional ones should be required. Even though it requires the four times faster clock frequency, it turns out that the bandwidth of the bio-signal stays narrow and gives little load to the reconfigurable amplifier.

The fully differential input signals, Sin+ and Sin- are applied to the capacitors, $C_{s}$, $C_{i}$, and $C_{f}$ represented by sampling capacitor, integrating capacitor, and feedback capacitor, respectively. Correlation between coefficient of loop factor and these capacitors, coefficients of the loop factor, and capacitors used in the modulator are presented in Tables 1- 3, respectively. These capacitors are implemented by MIM capacitors in terms of unit capacitor, 50 fF. The magnitude of the integrating capacitors, $C_{i1}$ and $C_{i2}$ is designed to be large, so that the input thermal noise (kT/C) should be suppressed as small as it could be during the first two clock phases. The fully differential outputs of the reconfigurable OPAMP with two conventional CMFB (Common Mode Feed Back) circuits drive the latched comparator, such that the latched comparator drives three cascade-connected DFFs (D Flip-Flop) to be able to generate a single bit stream signal. The twelve clock signals, as shown in Fig. 3, to control both sample mode and integration mode during the four cycles is generated by the delayed circuit with the non-overlapping clocks, q1 and q2. These clocks are utilized to sample and integrate the signals at each stage of DSM, respectively.

The sample and integration operation of the DSM for each cycle (clock phase) can be performed and distinguished by four different clocks (sel1, sel2, sel3, and sel4). The sample and integration mode for the first two cycles can be controlled by the clocks, sel1, sel2, p1q1, p2q1, p1p2q2, sam12, and sel12. In the same manner, the sample and integration mode for the second two cycles can be controlled by the clocks, sel3, sel4, p3q1, p4q1, p3p4q2, sam34, and sel34. During the sample mode of the first cycle, the switches of sel1, q1, p1q1, and sam12 turn on, where the switch, sam12 allows the sample capacitors, $C_{s2}$ and $C_{f2}$ to be charged to the common mode voltage. During the integration mode of the first cycle, the switches of sel1, q2, p1p2q2, and sam34 turn on, where the switch, sam34 allows the sample capacitors, $C_{s1}$ and $C_{f1}$ to be charged to the common mode voltage. In the similar manner, the sample mode of the second cycle enables the switches of sel2, q1,

p2q1, and sam12 to turn on. The integration mode of the second cycle allows the switches of sel2, q2, p1p2q2, and sam34 to turn on. The similar operation on the sample mode and integration mode of the third cycle and the fourth cycle is applied to control the switches, sel3, se4, p3q1, p4q1, p3p4q2, sam12, sam34, and sel34. The control signals, sel12 and sel34 are employed to select either two stage OPAMP during the first two clock phases or folded-cascode OPAMP during the second two clock phases, respectively. The DAC signals such as dacpx (dacp3, dacp4, dacp5, dacp6) and dacnx (dacn3, dacn4, dacn5, dacn6), as included in Fig. 2 are generated by the switching circuit. The signals, vonx (von3 ~ von6) and vopx (vop3 ~ vop6) are produced by the latched comparator with the digital buffers, DFFs. It is noted that the signals, vonx and vopx are specified at the output node of the latched comparator and DFFs. The circuit schematic of the single reconfigurable fully differential OPAMP is presented in Fig. 4. The constant trans-conductance bias circuitry not shown in the circuit diagram is utilized to provide the DC bias voltages, Vn1, Vn2, Vp1, and Vp2 for the folded-cascode OPAMP. It is noted that the switch, sel12 enables the output nodes (vop2, von2 in Fig. 3) of the two stage fully differential OPAMP architecture to connect to the nodes, int1- and int1+ as presented in Fig. 2 during the first two clock phases. The switch, sel34 allows the output nodes (von1, vop1 in Fig. 3) of the folded-cascode OPAMP to connect to the nodes, int1- and int1+ as presented in Fig. 2 during the second two clock phases.

As two different fully differential OPAMPs are utilized for the DSM, two different independent CMFB circuits are employed to provide both vcmfb1 and vcmfb2 to each OPAMP. Since the conventional DSM suffers from the input thermal noise, kT/C, the integrating capacitors, $C_{i1}$ and $C_{i2}$ are designed to be large during the first two clock phases so that the input thermal noise is to be suppressed. In order to drive the large integrating capacitors ($C_{i1}$ and $C_{i2}$) for the purpose of suppressing the input thermal noise, two-stage fully differential OPAMP with a wide output voltage swing and a compensation capacitor should be employed with the switch, sel12 to be enabled, as shown in Fig. 3. The other small integrating capacitors, $C_{i3}$ and $C_{i4}$ can be driven by the folded-cascode fully differential OPAMP with the switch, sel34 to be enabled during the second clock phases. Justification of employment of two different OPAMPs is as follows. Employment of only one OPAMP for 4^th order Delta-Sigma Modulator creates a problem of poor phase margin because of the capacitance difference at each integrator stage. In other words, the OPAMP should drive large capacitances ($C_{i1}$ and $C_{i2}$) during the first two clock cycles and small capacitances ($C_{i3}$ and $C_{i4}$) during the second two clock cycles. This unique situation requires the proposed DSM to employ two different OPAMPs which are capable of handling the phase margin problem properly. The phase margin of the modulator should be in the range of 60 to 90 degrees^[6]. If the phase margin exceeds 90 degrees, the integration speed of the integrator will be too slow to be able to complete the integrating operation within the integration time. The integration time is too critical to be neglected especially in the interleaving technique. The on-resistance (Ron) of the switches and the large capacitance (Cs and Cf) in the first and second stages allow a zero of the integrators described in (6) to move less than the unity gain frequency of the two stage OPAMP^[7]. This movement of the zero may result in the phase margin exceeding more than 90 degrees. Therefore the slow transient speed of the integrator may be unable to integrate the input signal within the integration time, as explained before. The on-resistance of the transmission gate employed as switches is 812Ω and the calculated zero based on (6) is 19.6 MHz.

The simulation results of the loop gain, the phase margin, and the unity gain frequency of the two stage OPAMP demonstrate 125 dB, 68 degrees, and 17 MHz, respectively. The simulation results of the loop gain, the phase margin, and the unity gain frequency of the folded-cascode OPAMP demonstrate 75 dB, 86 degrees, and 19 MHz, respectively. Since the simulated phase margins of two OPAMPs are less than 90 degrees, two OPAMPs should be able to integrate signals within the integration time.

III. EXPERIMENTAL RESULTS

The proposed DSM was implemented on a 180 nm 1 poly 6 metal CMOS process and the fabricated chip photograph is presented in Fig. 5. Placement of the digital cells with a guard ring was made on the top to isolate the analog cells (OPAMP and integration capacitors) on the bottom from digital switching signals. The integrating capacitors ($C_{i1}$ , $C_{i2}$ , $C_{i3}$ , and $C_{i4}$) implemented by MiM (Metal-Insulator-Metal) capacitor were placed in the lower left and right hand side of the chip, as shown in Fig. 5.

The symmetric placement of the analog cells on the bottom part of the chip is made with consideration of device matching. The layout area of the total circuit and the reconfigurable OPAMP with the trans-conductance bias circuit excluding pads occupies 850 µm x 950 µm and 300 µm x 70 µm, respectively. The FFT results on the output signal demonstrate the peak SNDR of 72.8 dB and the ENOB of 11.8bits, as presented in Fig. 6 and it is noted that the slope of the noise shaping curve between 1 kHz and 10 kHz is approximately +80 dB/dec, which confirms the basic functionality of the fourth order DSM. The thermal noise, KT/C can be observed at low frequency, so it can be reduced further by increasing the input capacitance.

The power consumption was measured to be 356 µW (analog power of 302 µW and digital power of 54 µW). Analog power consists of powers in gm constant bias circuit (115 µW), two OPAMPs(175 µW), and a comparator (12 µW). The measured digital power came from clock generator, transmission gate switches, and digital buffers. The measured SNDR as a function of the amplitude of the input signal is demonstrated in Fig. 7. The peak SNDR and dynamic range are measured to be 72.8 dB and 90 dB, respectively.

The ENOB (Effective Number Of Bit) is measured, as shown in Fig. 8, as a function of the input signal frequency ranging from 30 Hz to 1 kHz (bio-signal bandwidth) with the same clock frequency of 256 kHz. The ENOB remains almost constant (11.5-11.8 bit) over the bio-signal bandwidth. The Walden and Schreier FOM (Figure Of Merit) in (7) and (8), respectively are utilized in Table 4 to compare FOM of the proposed work with those of the conventional ones.

where BW, DR, and P stand for bandwidth, dynamic range, and power, respectively.

The power consumption and FOM(Walden) of the proposed work become half, compared with those of [1]^[1] which describes the fourth order DSM based upon two OPAMPs reconfigured. The FOM (Schreier) of the proposed work is more than 12 dB with respect to that of [1]^[1]. Compared with the continuous-time incremental DSM^[8], power of the proposed work is greater, but peak SNDR and FOM (walden) become higher. Even though the bio sensor application required low power DSMs^[9-11], they suffered from relatively lower SNDR and ENOB than those of the proposed work.

IV. CONCLUSION

A CMOS fourth order delta-sigma modulator with only one reconfigurable fully differential operational amplifier is proposed for the application of bio signal processing. The single reconfigurable fully differential amplifier, which can become either a two stage OPAMP (the first and second integrator) or a folded-cascode OPAMP (the third and fourth integrator), was employed not only to provide enough phase margin of the modulator, but also to reduce power consumption of the proposed DSM. This methodology enforces the proposed DSM to increase clock frequency four times with respect to that of the conventional ones due to four cycles reuse of the reconfigurable OPAMP. The proposed modulator is designed and implemented with CMOS 180 nm n-well 1 poly 6 metal process. The measurement results demonstrate the peak SNDR of 72.8 dB and the ENOB of 11.8 bits with an input signal frequency of 250 Hz, a sampling frequency of 256 kHz, an input signal bandwidth of 1 kHz, and an oversampling rate of 128. The ENOB of the proposed DSM remains constant (11.5 bits) up to 1 kHz of the bio-signal bandwidth. The total power dissipation was measured to be 356 µW at a supply voltage of 1.8 V.