| Title |
High-performance Sparsity-aware NPU with Reconfigurable Comparator-multiplier Architecture |
| Authors |
(Sungju Ryu) ; (Jae-Joon Kim) |
| DOI |
https://doi.org/10.5573/JSTS.2024.24.6.572 |
| Keywords |
Neural processing unit; sparse matrix; multiplier; weight pruning; hardware accelerator |
| Abstract |
Sparsity-aware neural processing units have been studied to exploit computational skipping on less important features in the neural network models. However, neural network layers typically show various matrix densities, so the hardware performance varies depending on the layer characteristics. In this paper, we introduce a reconfigurable comparator-multiplier architecture, so we can dynamically change the number of comparator/multiplier modules. The proposed reconfigurable architecture increases the throughput by 1.06-17.00× compared to the previous sparsity-aware hardware accelerators. |