| Title |
TRNG-PUF Integration Utilizing Programmable Delay Logics on FPGAs |
| Authors |
(Heehun Yang) ; (Jiho Park) ; (Jooseung Lee) ; (Hui-Myoung Oh) ; (Soonwoo Lee) ; (Hoyoung Yoo) |
| DOI |
https://doi.org/10.5573/JSTS.2024.24.3.240 |
| Keywords |
Field programmable gate array; ring oscillator; true random number generator; physically unclonable function |
| Abstract |
This paper introduces a novel TRNG-PUF structure using Programmable Delay Logic (PDL)-based Ring Oscillators (ROs), offering enhanced performance for both True Random Number Generators (TRNGs) and Physical Unclonable Functions (PUFs). Unlike previous approaches utilizing standard ROs, our design employs PDL to fine-tune the ROs, enabling effective harnessing of entropy for TRNGs and providing unique identification for PUFs. The proposed TRNG-PUF structure is implemented and tested on a Xilinx Artix-7 100T FPGA, demonstrating superior area efficiency and performance. In terms of hardware complexity, it showed the highest hardware efficiency among various designs. Particularly, compared to the conventional structure without shared sources, the proposed TRNG-PUF structure reduces the area of LUT and flip-flops by 41% and 24%, respectively. Moreover, the TRNG component of the structure is evaluated using the NIST SP 800-22 test, and it successfully passed all 15 tests. In contrast, previous TRNG-PUF designs only achieved partial success. Finally, the performance of the PUF is assessed through Hamming distance measurements, which showed excellent HDinter and comparable HDintra values. According to experimental results, the proposed TRNG-PUF structure is not only more area-efficient but also provides improved TRNG and PUF performance compared to previous TRNG-PUF designs. |