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Title 2 Lanes × 2.65-6.4 Gb/s Scalable IO Transceiver with Delay Compensation Technique in 65 nm CMOS Process
Authors (Goohyung Chung) ; (Kyoungub Cho) ; (Taehyoun Oh)
DOI https://doi.org/10.5573/JSTS.2024.24.3.184
Page pp.184-190
ISSN 1598-1657
Keywords CMOS; IO transceiver; scalable; delay compensation; pre-emphasis; FIR driver
Abstract A Delay compensation technique for implementing scalable high-speed logics has been proposed and its theoretical background has been analyzed fundamentally. Based on the scalable design methodology, the whole logics of proposed 2-channel transceiver operate successfully over the range of 2.65-6.4 Gb/s. The prototype chip has been fabricated in 65 nm CMOS process and occupies 1.02 mm2 die area. The transceiver consumes 72 mW/lane from 1.2 V supply. The measured eye-openings show 28.7% improvement vertically in Tx output by pre-emphasis at 6.4 Gb/s. The built-in Rx BER counter shows 0.25 unit interval (UI) horizontal eye-opening improvement at 10-9 BER in this speed.