| Title |
Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits |
| Authors |
(Prashanthi Metku) ; (Kyung Ki Kim) ; (Yong-Bin Kim) ; (Minsu Choi) |
| DOI |
https://doi.org/10.5573/JSTS.2021.21.6.483 |
| Keywords |
Null-convention logic; gate diffusion input; clockless design; transistor count reduction; simulation |
| Abstract |
Null Convention Logic (NCL) is a robust clock-less technique for designing asynchronous delay-insensitive circuits. The traditional complementary metal oxide semiconductor (CMOS) approach is often used for designing NCL circuits, which tends to occupy a large area. To address this issue, a low power design technique Gate Diffusion Input (GDI) is introduced for designing the NCL circuits. This GDI design methodology is the promising alternative for the static CMOS designs, which allows the reduction in area and power consumption while maintaining the low complexity of the logic design. In this paper, a novel GDI based NCL designs are proposed and designed. However, the voltage swings in the GDI approach leads to the considerable amount of voltage drop at the output. This limitation is addressed by using low threshold transistors where a voltage drop is expected, and high threshold transistors are used for the regenerative inverters at the output. The proposed approach has been verified by designing the NCL Ripple Carry Adder (RCA), Unpipelined multiplier, pipelined multiplier and Unpipelined ALU by using the GDI technique. These models are designed and simulated using Cadence Virtuoso and an average of 13.5 % reduction in the transistor count is observed for these GDI based NCL models when compared to the CMOS models. |