| Title |
A 28-nm CMOS 11.2-Gbps Receiver based on Adaptive CTLE and Adaptive 3-Tap DFE With Hysteresis Low-pass Filter |
| Authors |
(Myung-Hun Jung) ; (Yongsam Moon) |
| DOI |
https://doi.org/10.5573/JSTS.2021.21.3.229 |
| Keywords |
High-speed links; clock and data recovery (CDR); adaptive equalization; continuous-time linear equalizer (CTLE); decision-feedback equalizer (DFE) |
| Abstract |
This paper proposes a receiver design incorporating both an adaptive continuous-time linear equalizer (CTLE) and an adaptive decision-feedback equalizer (DFE). The CTLE utilizes a merged rectifier and error amplifier, improving the DC gain and reducing the current consumption. Offset cancelation of the CTLE is performed by adaptively adjusting the load resistance of a CTLE cell. The DFE adopts the technique of using a slave latch behind a current summer for the relaxed timing constraint but excludes other auxiliary circuits that perform a master-latch function. The proposed low-pass filter with a hysteresis can suppress the oscillation of the DFE tap coefficients and the data level in the steady state. Fabricated in 28-nm CMOS process, the prototype receiver shows that the measured BER is less than 10?14 at 10.4 Gb/s for an 18-inch FR4 trace and at 11.2 Gb/s for a 12-inch FR4 trace, respectively, with both the adaptive CTLE and the adaptive DFE activated. Operating at 11.2 Gb/s, the energy efficiency of the receiver is 5.36 pJ/bit. |