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Title [REGULAR PAPER] Low Noise, Low Power 5-channel Sonar Signal Conditioning Receiver with 1.5 MS/s - 12.5 MS/s 16-bit Sigma-delta ADC for Ocean Acoustic Measurements
Authors (Jong-Wan Jo) ; (Khuram Shehzad) ; (Deeksha Verma) ; (Sung-Jin Kim) ; (Young-Woo Park) ; (Kwan-Tae Kim) ; (Sang-Yun Kim) ; (YoungGun Pu) ; (Young-Goo Yang) ; (Keum-Cheol Hwang) ; (Dong-Hun Lee) ; (Hyung-Moon Kim) ; (Kang-Yoon Lee)
Page pp.326-342
ISSN 1598-1657
Keywords Sigma-delta ADC; low noise; band pass filter; sonar sensor; receiver; parallel-to-serial interface
Abstract This paper presents the design of a 5-channel receiver for ocean acoustic measurement in very noisy environments. When measuring distances in the ocean through sonar, the input signal level to the receiver can change drastically depending on the distance between the transmitter and objects. Thus, a receiver with low sensitivity and a wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for the high sensitivity of the receiver, a low noise pre-amplifier is proposed and implemented, ultimately achieving a noise of 29.6 nV/√Hz at 50 kHz. In addition, a Sigma-Delta Analog-to-Digital Converter (SD ADC) with variable sampling rates is proposed by using the clock splitting technique in the Sigma-Delta Modulator (SDM) core. In addition, the decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled so as to reduce the power consumption. Through the use of these techniques in the SD ADC, we can implement reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for multi-channel application, a Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The 5-channel receiver in this paper is implemented in a 0.18 μm CMOS process and the die area is 14.44 mm2. The total power consumption of this chip under a supply voltage of 2.4 V is 46.8 mW. The measured sensitivity and dynamic range are -100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively. The maximum phase error between five channels is measured to be ?0.8 °.