Mobile QR Code QR CODE

REFERENCES

1 
S. I. Shim, J. Jang, and J. Song, “Trends and future challenges of 3D NAND flash memory”, Proc. of IEEE International Memory Workshop (IMW), pp. 1-4, 2023.DOI
2 
K.-T. Park, M. Kang, D. Kim, S.-W. Hwang, B. Y. Choi, Y.-T. Lee, C. Kim, and K. Kim, “A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories”, IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 919-928, 2008.DOI
3 
H. Kim, S.-J. Ahn, Y. G. Shin, K. Lee, and E. Jung, “Evolution of NAND flash memory: From 2D to 3D as a storage market leader”, Proc. of IEEE International Memory Workshop (IMW), pp. 1-4, 2017.DOI
4 
C. Monzio Compagnoni, A. Goda, A. S. Spinelli, P. Feeley, A. L. Lacaita, and A. Visconti, “Reviewing the evolution of the NAND flash technology”, Proceedings of the IEEE, vol. 105, no. 9, pp. 1609-1633, 2017.DOI
5 
H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit cost scalable technology with punch and plug process for ultra high density flash memory”, Proc. of IEEE Symposium on VLSI Technology, pp. 14-15, 2007.DOI
6 
A. Goda, “Recent progress and future directions in NAND flash scaling”, Proc. of Non-Volatile Memory Technology Symposium (NVMTS), pp. 1-4, 2013.DOI
7 
J. Jang, H. Kim, W. Cho, H. Cho, J. Kim, S. Shim, Y. Goan, J. Jeong, B. Son, D. Kim, K. Shim, J. Lim, K. Kim, S. Yi, J. Lim, D. Chung, H. Moon, S. Hwang, J. Lee, Y. Son, U. Chung, and W. Lee, “Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory”, Proc. of Symposium on VLSI Technology, pp. 192-193, 2009.Google Search
8 
J. H. Kim, Y. Yim, J. Lim, H. S. Kim, E. S. Cho, and C. Yeo, “Highly manufacturable 7th generation 3D NAND flash memory with COP structure and double stack process”, Proc. of Symposium on VLSI Technology, pp. 1-2, 2021.Google Search
9 
J.-W. Park, D. Kim, S. Ok, J. Park, T. Kwon, H. Lee, S. Lim, S.-Y. Jung, H. Choi, T. Kang, G. Park, C.-W. Yang, J.-G. Choi, G. Ko, J. Shin, I. Yang, J. Nam, H. Sohn, S.-I. Hong, Y. Jeong, S.-W. Choi, C. Choi, H.-S. Shin, J. Lim, D. Youn, S. Nam, J. Lee, M. Ahn, H. Lee, S. Lee, J. Park, K. Gwon, W. Jeong, J. Choi, J. Kim, and K.-W. Jin, “A 176-stacked 512Gb 3b/cell 3D-NAND flash with 10.8Gb/mm$^2$ density with a peripheral circuit under cell array architecture”, Proc. of IEEE International Solid-State Circuits Conference (ISSCC), pp. 422-423, 2021.DOI
10 
Z. Huo, W. Cheng, and S. Yang, “Unleash scaling potential of 3D NAND with innovative Xtacking architecture”, Proc. of IEEE Symposium on VLSI Technology and Circuits, pp. 254-255, 2022.DOI
11 
X. Shen, Z. Xia, T. Yang, L. Liu, J. Dong, W. Zhou, C. Li, and Z. Huo, “Hydrogen source and diffusion path for poly-Si channel passivation in Xtacking 3D NAND flash memory”, IEEE Journal of the Electron Devices Society, vol. 8, pp. 1021-1024, 2020.DOI
12 
Y. Ouyang, S. Yang, D. Yin, X. Huang, Z. Wang, S. Yang, K. Han, and Z. Xia, “Excellent reliability of Xtacking bonding interface”, Proc. of IEEE International Reliability Physics Symposium (IRPS), pp. 1-6, 2021.DOI
13 
K. Ma, N. Bekiaris, C.-H. Hsu, L. Xue, S. Ramaswami, T. Ding, G. Probst, T. Wernicke, T. Uhrmann, and M. Wimplinger, “0.5 $\mu$m pitch wafer-to-wafer hybrid bonding at low temperatures with SiCN bond layer”, Proc. of IEEE 74th Electronic Components and Technology Conference (ECTC), pp. 331-336, 2024.DOI
14 
S. Lee, J. Lim, J. H. Kim, S. Cho, Y. K. Lee, and B. Choi, “High-density 3-D NAND cell array design with hybrid bonding”, IEEE Transactions on Electron Devices, vol. 70, no. 11, pp. 5638-5644, 2023.DOI
15 
D. B. L. Yolanda, “Wafer to wafer bonding to increase memory density”, Proc. of China Semiconductor Technology International Conference (CSTIC), pp. 1-4, 2022.DOI
16 
C. Zhao, L. Jin, D. Li, F. Xu, X. Zou, Y. Zhang, Y. Song, H. Wei, Y. Chen, C. Li, and Z. Huo, “Investigation of threshold voltage distribution temperature dependence in 3D NAND flash”, IEEE Electron Device Letters, vol. 40, no. 2, pp. 204-207, 2019.DOI
17 
D. Resnati, A. Mannara, G. Nicosia, G. M. Paolucci, P. Tessariol, A. S. Spinelli, A. L. Lacaita, and C. Monzio Compagnoni, “Characterization and modeling of temperature effects in 3-D NAND flash arrays–Part I: Polysilicon-induced variability”, IEEE Transactions on Electron Devices, vol. 65, no. 8, pp. 3199-3206, 2018.DOI
18 
J. Kang, J. Lee, Y. Yim, S. Park, H. S. Kim, E. S. Cho, T. Kim, J. H. Lee, J. Kim, J. Lim, S. Hur, S. J. Ahn, and J. Song, “Highly reliable cell characteristics with CSOB (channel-hole sidewall ONO butting) scheme for 7th generation 3D-NAND”, Proc. of IEEE International Electron Devices Meeting (IEDM), pp. 10.1.1-10.1.4, 2021.DOI
19 
Synopsys, Sentaurus Device User Guide, Version N-2023.09. Mountain View, CA, USA, 2023.Google Search
20 
D. Kim, and W. Shim, “SiGe-surrounded bitline structure for enhancing 3D NAND flash erase speed”, Applied Sciences, vol. 15, 2025.DOI
21 
P. Wang, F. Xu, B. Wang, B. Gao, H. Wu, H. Qian, and S. Yu, “Three-dimensional NAND flash for vector-matrix multiplication”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 4, pp. 988-991, 2019.DOI
22 
H.-N. Yoo, Y. Yang, M.-K. Park, W. Y. Choi, and J.-H. Lee, “Analysis of GIDL erase characteristics in vertical NAND flash memory”, Journal of Semiconductor Technology and Science, vol. 23, no. 3, pp. 196-201, 2023.DOI
23 
J. Lee, Y. Kim, Y. Shin, S. Park, D. Kang, and M. Kang, “Analysis of cell current with abnormal channel profile in 3D NAND flash memory”, Journal of Semiconductor Technology and Science, vol. 24, no. 2, pp. 138-143, 2024.DOI
24 
H. S. Yun, and J. K. Park, “Improving Z-interference and program disturbance in 3D NAND flash memory using asymmetric program-pass voltage”, Journal of Semiconductor Technology and Science, vol. 24, no. 6, pp. 565-571, 2024.DOI
25 
D. Wu, H. You, X. Wang, S. Zhong, and Q. Sun, “Experimental investigation of threshold voltage temperature effect during cross-temperature write-read operations in 3-D NAND flash”, IEEE Journal of the Electron Devices Society, vol. 9, pp. 22-26, 2021.DOI
26 
M. A. Kumar, and B. Ray, “Cross-temperature reliability of 3D NAND: Cell-to-cell variability analysis and countermeasure”, Proc. of IEEE International Reliability Physics Symposium (IRPS), pp. P25.MR-1-P25.MR-7, 2024.DOI
27 
T. Tanzawa, T. Tanaka, S. Tamada, J. Kishimoto, S. Yamada, K. Kawai, T. Ichikawa, P. Chiang, and F. Roohparvar, “A temperature compensation word-line voltage generator for multi-level cell NAND flash memories”, Proceedings of ESSCIRC, pp. 106-109, 2010.DOI
28 
D. G. Refaldi, G. Malavena, L. Chiavarone, A. S. Spinelli, and C. Monzio Compagnoni, “Origin of the temperature dependence of gate-induced drain leakage-assisted erase in three-dimensional NAND flash memories”, Micromachines, vol. 15, 2024.DOI
29 
J. Kim, H. Jo, Y. Cho, H. Shim, J. Sim, and H. Shin, “Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide”, IEICE Electronics Express, vol. 19, no. 24, 2022.DOI
30 
L. Lopez, P. Masson, D. Née, and R. Bouchakour, “Temperature and drain voltage dependence of gate-induced drain leakage”, Microelectronic Engineering, vol. 72, no. 1-4, pp. 101-105, 2004.DOI