I. INTRODUCTION

The explosive growth of data driven by modern applications such as artificial intelligence and cloud computing has created an unprecedented demand for high-density, high-speed non-volatile memory, particularly NAND Flash ^{[1- 3]}. Early planar NAND Flash technology increased integration density by shrinking cell dimensions. Ultimately, this led the 2D planar architecture to face fundamental physical limits ^[4]. To overcome the scaling limits of 2D planar technology, a 3D vertical stacking architecture was proposed by forming vertical channels and stacking word-lines (WLs) ^{[5- 7]}. As the number of stacked layers increased, the area efficiency of the cell array improved. However, scaling down the peripheral circuit area proved difficult because it includes analog circuits and high-voltage devices. This limitation acted as a bottleneck in reducing the overall die size. To address this spatial inefficiency and maximize integration density, the cell-over-peripheral (COP) architecture which places the memory array above the peripheral circuits was introduced ^{[8, 9]}.

While the COP approach improved die efficiency, it introduced new manufacturing and performance challenges. Along with the need for greater bit density, there is a growing requirement for faster input-output (I/O) speeds. However, the COP architecture exerts a significant thermal burden on the peripheral circuits, as the memory cell fabrication follows the peripheral circuit formation. This excessive heat exposure degrades transistor performance, creating a major obstacle to realizing high-speed I/O operations. To overcome this critical thermal problem, hybrid bonding technology has emerged as the core infrastructure for next-generation 3D NAND ^{[10- 13]}.

This method involves fabricating the high-temperature cell array wafer and the optimized peripheral circuit wafer separately, then bonding them via high-density copper-to-copper interconnects. This wafer-to-wafer process decoupling fundamentally resolves the thermal budget constraints on peripheral circuit transistors, allowing for independent process optimization of both layers. Furthermore, this architecture enables unprecedented interconnect density, supports ultra-high layer stacking, and enhances I/O speed ^{[14, 15]}.

Fig. 1. Vertical thermal gradient during GIDL erase operation in a hybrid bonding 3D NAND.

Fig. 2. An example of temperature-induced distribution variation on the Vth distribution and read margin in TLC NAND Flash.

However, the high-speed I/O operation inevitably intensifies self-heating during device operation, resulting in a vertical temperature gradient along the NAND string during gate-induced drain leakage (GIDL) erase operation, as shown in Fig. 1. Moreover, high-speed I/O-induced heat accumulation in the peripheral circuits exposes the top cells to substantially elevated temperatures, whereas the bottom cells remain at a relatively low temperature.

Overall, as temperature-induced effects superimpose onto existing process variations, the $V_{th}$ distribution width increases significantly ^[16]. This increased distribution width can severely compromise the memory window and read margin required for high-density triple-level cell (TLC) and quad-level cell (QLC) operations ^[17], as shown in Fig. 2.

In this study, to analyze and address these temperature-induced issues, we conducted a comprehensive investigation on both the body contact spacer (BCS) structure utilizing bulk erase and the channel-hole sidewall ONO butting (CSOB) structure utilizing GIDL erase, based on hybrid bonding ^[18]. We focused on the WLs adjacent to the bonding interface, which experiences elevated temperatures due to the underlying peripheral circuits. We investigated the overall $V_{th}$ variations by distinguishing between scenarios where the program/erase temperature matches the read temperature and mismatched scenarios where the read temperature varies while the program/erase temperature remains fixed. Finally, we propose voltage control schemes to mitigate the broadened $V_{th}$ distribution by applying a bias greater than 0 V to the WLs adjacent to the peripheral circuits during the erase operation and utilizing a pass voltage ($V_{pass}$) lower than the conventional level during the read operation. We verified the effectiveness of the proposed approaches by modeling a single 64-WL 3D NAND string based on the hybrid bonding structure using the Sentaurus TCAD simulation tool from Synopsys ^[19].

II. DEVICE STRUCTURE AND SIMULATION METHODOLOGY

To conduct a comparative analysis of temperature dependence regarding different erase mechanisms in the hybrid bonding structure, we modeled both the BCS structure utilizing bulk erase and the CSOB structure utilizing GIDL erase. Fig. 3(a) depicts the conventional BCS structure. A distinguishing feature of this design is that the bottom of the vertical channel is directly connected to the p-substrate region, doped with boron at a concentration of $1\times 10^{15}\text{ cm}^{-3}$, allowing for direct hole injection from the substrate into the channel during the erase operation.

Fig. 3. Structure cross-sectional views of (a) BCS and (b) CSOB used in the simulation.

Fig. 3(b) illustrates the CSOB structure optimized for the hybrid bonding architecture. In this configuration, the floating channel is disconnected from the substrate. Both its top and bottom ends are plated by n+ poly-Si doped with arsenic at a concentration of $1 \times 10^{20}\text{ cm}^{-3}$ ^[20].

To facilitate hole generation during the erase operation, GIDL transistors (GIDL TR) are positioned adjacent to the string-select line (SSL) and ground-select line (GSL). The vertical dimensions were set with a WL length of 30 nm and a spacer length of 20 nm ^[20].

The material composition and dimensions of the memory cell stack were kept identical for both structures, as detailed in the inset of Fig. 3. The A-A′ cross-section shows the layer thicknesses in the radial direction, consisting of a 50 nm thick tungsten gate, an 8 nm blocking oxide, a 7 nm silicon nitride charge trap layer, and a 5 nm tunneling oxide ^{[21, 22]}. The Poly-Si channel is 8 nm thick, and the core is filled with an oxide filler with a radius of 22 nm.

The carrier recombination model was based on Shockley-Read-Hall (SRH) processes considering doping dependence, while band-to-band tunneling (BTBT) was modeled using the Hurkx formulation. Carrier transport employed the Philips unified mobility (PhuMob) model calibrated for arsenic doping, incorporating a high-field saturation correction based on the electric field normal to the interface (Enormal) to capture velocity saturation effects ^[23]. Within the nitride layer, we introduced donor trap energy levels at 2.5 eV below the conduction band and acceptor traps at 1.0 eV below the conduction band. The density for each trap type was set to $1 \times 10^{19}\text{ cm}^{-3}$, with electron and hole capture cross-sections of $1\times 10^{-13}\text{ cm}^2$.

Table 1 summarizes the specific bias conditions for the BCS structure ^[24]. For the program operation, the program voltage ($V_{PGM}$) was set to 14 V. The operation timing consists of a 30 $\mu\text{s}$ execution phase, with ramp-up and ramp-down times of 1 $\mu\text{s}$ each. The erase operation employs an erase voltage of 14 V. The sequence comprises a 50 $\mu\text{s}$ ramp-up phase, followed by a 1 ms execution phase, and concludes with a 20 $\mu\text{s}$ ramp-down phase. Table 2 details the bias conditions for the CSOB structure ^[24]. The program operation follows the same timing and voltage settings as the BCS structure with a $V_{PGM}$ of 14 V, a 30 $\mu\text{s}$ execution time, and 1 $\mu\text{s}$ ramps. For the erase operation, the 50 $\mu\text{s}$ ramp-up and 20 $\mu\text{s}$ ramp-down times remained consistent along with the 14 V erase voltage. The execution time was extended to 2 ms to ensure sufficient BTBT generation. The erase operation is performed on the entire string, while the program operation is selective to the target WL.

To emulate the vertical thermal gradient, the temperature of the bottom cells was fixed at 290 K, while the temperature of the top cells was varied. As summarized in Table 3, we evaluated the device characteristics under distinct thermal scenarios for program and erase operations employing both CSOB and BCS structures ^{[25- 27]}. For the program operation, we focused on the mismatched scenario, where the program temperature was fixed at 300 K while the read temperature was swept from 290 K to 350 K. This exclusion of the matched scenario is based on the fact that the program operation relies on the Fowler-Nordheim tunneling mechanism, which is driven by the electric field and exhibits negligible temperature dependence ^[28]. For the erase operation, we investigated both mismatched and matched scenarios. In the mismatched case, the erase temperature was held at 300 K with a varying read temperature. The matched case involved sweeping both erase and read temperatures from 300 K to 350 K to simulate device operation under a high-temperature environment.

The simulation results corresponding to the thermal scenarios in Table 3 are presented in Fig. 4. The left column (a), (c), (e) of this figure represents the BCS structure. The right column (b), (d), (f) corresponds to the CSOB structure. As illustrated in Fig. 4, a significant shift in $V_{th}$ is observed in the top WLs adjacent to the peripheral circuits as the peripheral circuits temperature increases. The erase-matched scenario in Fig. 4(a) and (b) shows that the CSOB structure exhibits a substantial $V_{th}$ shift of 850 mV while the BCS structure shows a much smaller shift of 200 mV. This indicates a significantly higher temperature dependence in the CSOB structure. For the mismatched scenarios where the operation temperature is fixed at 300 K, the $V_{th}$ shifts are relatively moderate. As shown in Fig. 4(c) and (d) for the erase-mismatched scenario both structures exhibit a shift of 80 mV. In the program-mismatched scenario presented in Fig. 4(e) and (f) the shifts are limited to 100 mV for the BCS structure and 80 mV for the CSOB structure. Consistent with prior studies, these results indicate that although the high-temperature erase effect is dominant, the impact of read temperature variation is non-negligible and contributes significantly to the total $V_{th}$ variation ^[29]. The vertical thermal gradient discussed earlier exposes cells within a single string to varying temperatures and inevitably leads to a broadening of the overall $V_{th}$ distribution. When compounded by existing process variations, this temperature-induced widening further exacerbates the distribution spread. As shown in Fig. 2, this degradation can severely compromise the read margin required for high-density storage technologies such as TLC and QLC, which demand precise $V_{th}$ control. Furthermore, the enhanced erase efficiency at elevated temperatures can lead to an over-erase phenomenon. This unintended deep erasure imposes excessive stress on the tunneling oxide, potentially degrading the long-term cycling endurance of the device ^[29]. Since the CSOB structure utilizes the GIDL erase mechanism which is inherently sensitive to temperature, it exhibits higher temperature dependence compared to the BCS structure ^[30]. Consequently, it is more susceptible to this excessive stress, leading to a more severe degradation in endurance. To address this issue of broadened $V_{th}$ distribution, we introduce an optimized voltage scheme designed to mitigate these thermal effects and effectively narrow the distribution width.

Fig. 4. Simulation results of I-V characteristics for BCS and CSOB structures before optimization under (a), (b) erase-matched (c), (d) erase-mismatched, and (e), (f) program-mismatched scenarios.

III. PROPOSED OPTIMIZATION VOLTAGE SCHEME FOR MITIGATING THERMAL EFFECTS

To address the $V_{th}$ spreading issue, we introduce a voltage control scheme optimized for temperature variations. As confirmed in Section II, the elevated temperature of the top WLs adjacent to the peripheral circuits causes excessive erase and induces instability in the read operation following program and erase operations. To mitigate these effects, our optimization strategy includes two key approaches tailored to specific thermal scenarios. First, Fig. 5(a) illustrates the optimized bias voltage control scheme designed to address the over-erase phenomenon in the erase-matched scenario. The conventional method, indicated by the black line, grounds the WLs during the erase operation. In contrast, the proposed voltage control scheme, represented by the red line, applies a gradient bias voltage greater than 0 V to the upper WLs during the erase pulse. Specifically, the highest bias is applied to the topmost WLs where the thermal impact is most severe, and the voltage magnitude is gradually decreased toward the lower WLs. This positive bias reduces the potential difference between the gate and the channel, thereby suppressing excessive hole injection and effectively preventing the device from entering a deep-erase state.

Fig. 5. Proposed optimization voltage schemes. (a) Gradient bias scheme for the match scenario. (b) Read voltage adjustment scheme for the mismatch scenario.

Second, for the mismatched scenarios where read stability is critical, we adopted a read voltage adjustment scheme as depicted in Fig. 5(b). This figure compares the conventional read scheme, shown as the black line, with the proposed approach, shown as the red line, where the $V_{pass}$ applied to the adjacent WLs is adaptively lowered during the read operation. This reduction in $V_{pass}$ effectively neutralizes the resulting $V_{th}$ shifts.

Fig. 6. Optimized I-V characteristics of BCS and CSOB structures under (a), (b) erase-matched (c), (d) erase-mismatched, and (e), (f) program-mismatched scenarios.

Fig. 6 demonstrates the efficacy of these proposed voltage control schemes under the same thermal scenarios analyzed previously. Fig. 6(a) and (b) present the I-V characteristics under the erase-matched scenario. The optimized bias voltage control scheme illustrated in Fig. 5 drastically suppressed the substantial $V_{th}$ shift in the CSOB structure. The shift decreased from an original 850 mV to 10 mV. Similarly, the BCS structure exhibited a reduction from 200 mV to a negligible 10 mV. This uniformly minimized shift confirms that controlling the erase potential effectively neutralizes the temperature dependence difference between CSOB and BCS structures.

For the mismatched scenarios, the optimized read scheme proved highly effective. Fig. 6(c) and (d) demonstrate that under the erase-mismatched scenario, the $V_{th}$ shifts for both structures were reduced to 10 mV. This is a substantial improvement from the pre-optimization value of 80 mV. Furthermore, regarding the program-mismatched scenario shown in Fig. 6(e) and (f), the shifts were successfully minimized to 10 mV for both structures compared to the initial range of 100 mV. These results indicate that the proposed optimization strategy can reduce the $V_{th}$ shift to 10 mV across all thermal scenarios. This applies regardless of the structural differences between BCS and CSOB. By narrowing the distribution width, this approach secures the critical read margin required for high-density TLC and QLC 3D NAND flash memories. Moreover, the proposed voltage scheme mitigates the over-erase phenomenon. This reduction in excessive stress on the tunneling oxide offers a promising solution to enhance the long-term cycling endurance of hybrid bonding-based devices.

IV. CONCLUSIONS

In this work, we proposed a novel voltage control scheme to overcome the $V_{th}$ spreading issue in hybrid bonding 3D NAND. This issue is primarily caused by vertical thermal gradients. Our approach utilizes a gradient erase bias and an adaptive read voltage. Simulation results showed that the temperature-induced $V_{th}$ shift could be reduced from 850 mV to 10 mV compared to the conventional voltage control scheme. This enhancement in distribution characteristics secures sufficient read margins for high-density storage. Furthermore, it improves long-term cycling endurance by mitigating the over-erase phenomenon.