I. INTRODUCTION

The relentless miniaturization of semiconductor devices has driven continuous advancements in fabrication techniques and material engineering ^{[1- 3]}. A critical challenge in this progression is the reduction in dielectric layer thickness, which has become a bottleneck in achieving both performance and reliability ^{[4- 6]}. As the thickness of dielectric layers approaches and falls below 2 nm, quantum tunneling effects become increasingly pronounced, resulting in a significant escalation of leakage current ^[7]. This leakage not only degrades device performance but also adversely impacts power efficiency and thermal stability–key considerations in modern electronic systems. To address this issue, high-k dielectric materials, which possess higher dielectric constants than conventional SiO₂, have been extensively studied and implemented in semiconductor devices. Materials such as HfO₂ and ZrO₂ have demonstrated improved performance due to their ability to maintain capacitance at reduced thicknesses. However, an inherent trade-off exists: many high-k materials exhibit narrow energy bandgaps, leading to elevated leakage currents. Consequently, the search for dielectrics with both high dielectric constants and low leakage currents remains a persistent challenge in the field. One promising approach to overcoming this trade-off is the use of composite dielectric structures. In particular, this study explores a triple-layer dielectric configuration that intercalates TiO₂, known for its high dielectric constant and small energy bandgap, between layers of SiO₂ or HfO₂ ^[8]. By leveraging the complementary properties of these materials, the triple-layer structure seeks to balance the competing demands of minimizing leakage current while maximizing overall device performance.

To evaluate this approach, MOS capacitors and MOSFETs with varying dielectric configurations were simulated and analyzed. Initial band diagram studies reveal that devices using triple-layer dielectrics (Fig. 1(b)) form energy barriers capable of reducing leakage current, whereas single-layer TiO₂ configurations (Fig. 1(a)) lack such barriers due to its higher work function. The incorporation of TiO₂ in a triple-layer arrangement effectively suppresses leakage current while maintaining the high capacitance benefits of high-k materials. These findings highlight the potential of composite dielectrics to address the limitations of single-layer high-k materials.

This paper introduces a novel triple-layer dielectric configuration and provides a comprehensive experimental framework for its evaluation. The proposed structure not only mitigates leakage current but also enhances device reliability and scalability, offering a robust solution for next-generation semiconductor devices.

II. EXPERIMENTAL DETAILS

Fig. 1(a) shows the band diagram of the Gate metal/Dielectric/Si substrate when a high-k dielectric with a high dielectric constant is applied. In Fig. 1(a), Ti is used as the gate metal to illustrate an extreme example. As can be seen from the band diagram, when a dielectric with a small band gap is applied, the barrier between the gate and the Si channel becomes lower, which can easily cause leakage. Fig. 1(b) shows the band diagram structure of the triple dielectric layer proposed in this study. The proposed structure is to suppress leakage by setting dielectrics with a high band gap like barriers on both sides, and SiO₂ is used as an example in this Fig. 1(a)

In the case of an insulating layer with a high band gap, the dielectric constant is lower, so the capacitance characteristics are naturally reduced compared to when using a single high-k dielectric. However, the three-layer dielectric structure follows a parallel calculation [C_total = (1/C_barrier + 1/C_high-k + 1/C_barrier)^-1], resulting in higher capacitance characteristics than a layer with a low dielectric constant. Fig. 2 shows the capacitance values for various structures.

Fig. 1. The band diagrams of an MOS capacitor under the flat-band condition for three different dielectrics configurations.

Fig. 2. The 5nm insulating layer was formed using a combination of SiO₂, HfO₂, and TiO₂. The capacitance ratio was compared to a 5 nm SiO₂ reference, based on the proportion of each material in the layer.

III. RESULTS AND DISCUSSIONS

Fig. 2 shows the capacitance ratio compared to 5 nm SiO₂ for each case where the 5nm insulating layer is composed of (a) SiO₂ only, (b) HfO₂ only, (c) TiO₂ only, (d) HfO₂ with a 1nm SiO₂ barrier, (e) TiO₂ with a 1nm SiO₂ barrier, and (f) TiO₂ with a 1nm HfO₂ barrier. In this study, we aimed to compare the characteristics of transistors by characterizing the capacitance based on a 5nm insulating layer. The gate dielectric thickness was set to 5 nm considering the current technology node of semiconductor devices, where the device pitch is approximately 40-50 nm and the gate line width is only around 20 nm. Furthermore, fabrication processes for depositing such thin dielectric layers using ALD are already well-established in the semiconductor industry. Therefore, we consider the choice of a 5 nm gate dielectric to be a realistic and practical assumption. In addition, for practical implementation, the triple-layer dielectric stack can be realized through sequential ALD deposition of SiO₂ (bottom), TiO₂ (middle), and HfO₂ (top) layers under typical ALD conditions. During this process, interface engineering becomes crucial since oxygen vacancy formation at the TiO₂/SiO₂ interface and inter-diffusion at the TiO₂/HfO₂ boundary may affect long-term device reliability and leakage behavior. These effects can be mitigated through post-deposition O₂ annealing and plasma surface treatment during fabrication ^{[9, 10]}. It should also be noted that the present work focuses mainly on the impact of barrier height among the dielectric stacks; therefore, the analysis and discussion are primarily based on this aspect.

We first confirmed the expected result that the capacitance value increases as the dielectric constant increases when each structure consists of a single insulating layer. To address the leakage issue caused by the band gap of high-k dielectrics, we also examined the structure with a 1nm SiO₂ barrier added on both sides. While the capacitance of this structure was lower than that of TiO₂ only or HfO₂ only, it showed more than twice the capacitance compared to SiO₂.

In the triple dielectric structure, the goal is to achieve higher capacitance compared to SiO₂ only, resulting in better current characteristics, while simultaneously reducing gate leakage current–an issue caused by the lower bandgap–through the effect of the barrier. To verify this, a transistor structure was formed, and current-voltage characteristics were examined by TCAD simulation ^{[11, 12]}. Since the primary objective was to investigate the impact of dielectric structure modifications and evaluate their advantages and disadvantages, it was also necessary to examine the tunneling current that could occur within the dielectric layers. Therefore, three tunneling models–Fowler-Nordheim (FN) Tunneling, Direct Tunneling, and Band-to-Band (B2B) Tunneling–were incorporated to ensure that all major tunneling mechanisms were properly considered in the simulation. The structure for analyzing electrical characteristics is composed of titanium with a thickness of 40 nm, while the silicon substrate doped with boron at a concentration of 1 × 10¹⁷ cm^-3, including source and drain regions doped with arsenic at a concentration of 1.0 × 10¹⁹ cm^-3. The channel length was intentionally set to 200 nm. This was because the primary focus of this study was to investigate gate-induced leakage rather than body-related leakage. By using a relatively long channel, the probability of tunneling events under the applied gate bias was assumed to be more clearly observable. To evaluate the effectiveness of the triple-layer dielectric structure in mitigating the leakage current issue associated with high-k dielectrics, the current flowing from the gate to the substrate was measured over a voltage range of 1 V to 3 V. Although the applied voltage to the gate region (1.8 V) is higher than that typically used in modern logic devices, it was deliberately chosen to emphasize relative trends and to clearly differentiate the effects of different dielectric combinations, rather than to reproduce the exact operating conditions. Additionally, the difference in current levels flowing from the drain to the source, within the voltage range of 0V to 4V during a voltage sweep, was observed to determine the I_D-V_G curve to evaluate device performance.

Fig. 3 presents the results of the electrical characteristics of the device analyzed using simulation. Fig. 3(a) shows the structure of the Field Effect Transistor (FET) fabricated using the previously mentioned method, and the characteristics were compared and analyzed by varying the gate dielectrics.

Fig. 3(b) illustrates the gate leakage current in this structure. The difference in gate leakage current at the same 5nm thickness is observed, with the largest band gap material, SiO₂, exhibiting the lowest leakage current, while TiO₂ and HfO₂, which have smaller band gaps, show higher leakage currents. Additionally, the triple dielectric structure using SiO₂ as a 1nm barrier layer on both sides shows an improvement in leakage current as expected. Figs. 3(c) and 3(d) show the variation in drain current with respect to changes in drain voltage for TiO₂-based and HfO₂-based dielectrics, respectively. As the capacitance increases, meaning the dielectric constant is higher, the amount of charge accumulating in the channel increases, leading to a higher current. Therefore, compared to SiO₂-only structures, higher currents can be expected in TiO -only and HfO -only structures, which is confirmed by the results. The results indicate that while the increased barrier height suppresses leakage and contributes to improve on-current, the thin dielectric layers also lead to tunneling-induced degradation, resulting in a reduced breakdown voltage. Additionally, in the case of the triple dielectric structure proposed in this study, although a barrier is used to reduce leakage, the capacitance is still larger than that of SiO₂-only structures, resulting in an improved drain current, as shown in the graph. Furthermore, the revised V_g-I_d characteristics confirm that the triple dielectric stack has minimal impact on overall device switching behavior; the on-current follows a similar trend to the V_d-I_d characteristics, while the off-current, threshold voltage (V_t), and subthreshold swing remain largely unchanged. It should also be noted that the present simulation assumes an ideal interface, and non-ideal stack properties such as trap-assisted tunneling (TAT) or interface-state-related effects may further influence the leakage behavior in practical devices. Therefore, future experimental work and detailed interface characterization are required to validate the proposed structure. In ultra-thin SiO₂ layers (~1 nm), localized trap-assisted tunneling can significantly increase leakage current by providing low-energy conduction paths, effectively reducing the barrier height between the gate and the channel. Although the TCAD model used in this work assumes ideal interfaces, practical devices may experience higher leakage and slightly reduced capacitance improvement due to such non-ideal trap states. This highlights the need for proper interface engineering during ALD growth, including optimized oxygen partial pressure and plasma pre-treatment, to suppress trap formation and ensure reliable dielectric performance in experimental implementations.

Fig. 3. (a) The transistor structure used for device characteristic validation, (b) gate leakage current for each dielectric structure based on this, and (c)-(d) I_D-V_G curves for the triple dielectric structure.

IV. CONCLUSIONS

In this study, a triple-layer dielectric device, achieved by depositing multiple dielectric layers using different materials was simulated and evaluated, demonstrating the advantages of this approach in enhancing the electrical performance of semiconductor devices. It has been shown that optimizing the balance between leakage current and dielectric constant can significantly enhance the overall performance of devices compared to those using single layer dielectrics. Additionally, the reduction in leakage current contributes to improved efficiency and reliability of semiconductor devices. The ability to tailor electrical characteristics to meet diverse application and performance requirements offers greater flexibility in device design. Furthermore, the versatility of modifying the dielectric structure enables its application across a broad spectrum of semiconductor devices, thereby proving beneficial in various sectors of the semiconductor industry.