| Title |
A 1.12-ps Resolution Flash ADC-assisted Coarse-to-fine Time-to-digital Converter with Adaptive Reference-voltage Calibration and Digital Linearity Correction |
| Authors |
(Solmon Shin) ; (Hyunwoo Son) ; (Youngsik Kim) ; (Shinwoong Kim) |
| DOI |
https://doi.org/10.5573/JSTS.2025.25.6.711 |
| Keywords |
Time-to-digital converter (TDC); coarse-to-fine-conversion architecture; ADC-assisted TDC; ; reference-voltage calibration; digital linearity correction |
| Abstract |
This paper proposes a high-resolution time-to-digital converter (TDC) featuring a coarse-to-fine architecture that integrates a 13-stage ring oscillator for coarse measurement and a flash ADC for sub-phase fine correction.
To address differential nonlinearity (DNL) induced by fixed ADC reference voltage, we introduce two calibration techniques: an adaptive reference voltage calibration loop?comprising a peak detector, comparator, delta-sigma modulator, and 1-bit DAC?that dynamically aligns the flash ADC reference to the actual input peak across ZONEs (coarse quantization regions), and a digital linearity correction that subdivides each of the 13 ZONEs into four sub-ZONEs (totaling 52) with lookup-table-based error compensation. Post-layout simulations in 28 nm CMOS demonstrate a time resolution of 1.12 ps, conversion range of 63 ns, conversion time of 5.6 ns, DNL of ±1.5 LSB, INL of ±5 LSB, and power consumption of 5.42 mW within a 0.625 mm2 core area. These results confirm the suitability of TDC for applications requiring both high speed and high accuracy. |