| Title |
A Fourth-order ∆Σ Modulator Using Hybrid Noise-shaping SAR ADC with Digital Cancellation |
| Authors |
(Sung-Hoon Cho) ; (Myunglae Choo) ; (Byung-Guen Lee) |
| DOI |
https://doi.org/10.5573/JSTS.2025.25.5.616 |
| Keywords |
Delta-sigma modulator; noise shaping (NS); successive approximation register (SAR); residue; OpAmp sharing; gm-C integrator |
| Abstract |
A hybrid delta-sigma (∆Σ) modulator is proposed to achieve additional second-order noise shaping via feedback paths consisting of the 1-bit fine quantizer output (DFine) and integrated residues. A 5-dB noise suppression is obtained through digital cancellation using DFine without causing noise leakage. In a 180-nm CMOS process with a sampling rate of 12 MHz and oversampling ratios (OSRs) of 16 and 32, the ∆Σ modulator achieved signal-tonoise and distortion ratios (SNDRs) of 92.9 and 96.7 dB and power consumption of 1.3 mW from a 1.8-V supply, showing improved noise suppression and power efficiency. |