| Title |
An Automatic Place-and-route Method for CDAC Arrays with Parasitic Effect Suppression |
| Authors |
(Wenjie Yang) ; (Yanning Chen) ; (Dong Zhang) ; (Fang Liu) ; (Yang Zhao) ; (Fang Ni) ; (SongChao Zhu) ; (Xiangyu Meng) |
| DOI |
https://doi.org/10.5573/JSTS.2025.25.5.517 |
| Keywords |
Automatic layout; auto-routing; capacitor arrays; high matching; EDA |
| Abstract |
In order to solve the problems of low efficiency of capacitive array layout design and parasitic effects affecting the matching degree in high-precision SAR ADCs, this paper proposes an automatic placement and routing method for capacitive digital-to-analog converter (CDAC) based on EDA technology. By routing the bottom plate beneath the bottom metal of the capacitor and integrating the shield structure, the parasitic coupling effect between the top plate and the bottom plate is significantly reduced. Combined with the co-centroid layout and the inter-bit staggered arrangement strategy, the horizontal parasitic coupling of adjacent capacitor bottom plates is effectively suppressed. The algorithm adopts a layered routing mechanism, uses Metal3 and Metal4 to realise the separation of horizontal and vertical routing, and optimises the matching characteristics by dynamically adjusting the intercolumn distribution of capacitors, and the effective number of bits (ENOB) can increase by up to 0.38 bits after adding a shielding layer. Experimental results show that the layout generation time of the proposed method is only 0.85-14.26 seconds, the ENOB can reach 99.20%-99.77% of the ideal value in the 8-13 bit CDAC design. This method realises the second-level automatic generation of high-precision capacitor arrays, and provides an efficient EDA solution for high-performance ADC design. |