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Title Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes
Authors (Moonjeong Choi) ; (Juhwan Park) ; (Seoungyeol Choi) ; (Kyungbae Kwon) ; (Yeji Lee) ; (Wonyeong Jang) ; (Jongwook Jeon)
Page pp.215-227
ISSN 1598-1657
Keywords Gate-all-around FET; process design kit; parasitic extraction; benchmark; interconnect
Abstract In this work, circuit-level benchmarks were performed on Copper(Cu), Tungsten(W), Cobalt(Co), Ruthenium(Ru), and Doped-multilayer-graphene (DMLG), which are various metallic material options applicable to the wire process at the late semiconductor process nodes. For the transistor, a multi-nanosheet field-effect-transistor (mNS-FET) with gate-all-around (GAA) technology was used, and the power and performance characteristics of the inverter ring oscillator circuit were analyzed assuming a 3 nm process node. In addition, various wire metal options for circuit layout were evaluated by varying fan-out number and wire length. As a result, the speed is fastest for Co and the speed reduction is smallest for DMLG in FO1 50CPP.