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Title Device Optimization for Short-channel Effects Suppression in UFETs
Authors (Sung-Su Yoon) ; (Ja-Yun Ku) ; (Khwang-Sun Lee) ; (Dae-Han Jung) ; (Dong-Hyun Wang) ; (Jun-Young Park)
DOI https://doi.org/10.5573/JSTS.2023.23.3.183
Page pp.183-188
ISSN 1598-1657
Keywords Buried gate; direct tunneling; gate leakage; silicon-on-nothing (SON); U-shaped channel FET (UFET); TCAD simulations
Abstract Excessively reducing gate length leads to an increase in off-state current (IOFF) due to severed short-channel effects (SCEs). 3D device architectures such as FinFETs, gate-all-around (GAA) FETs, and U-shaped channel FETs (UFETs), have been proposed in efforts to minimize the SCEs. However, increasing IOFF due to gate leakage and junction leakage is difficult to avoid. In this context, a device optimization of modern UFETs is proposed to suppress the unwanted IOFF. 3-dimensional (3-D) numerical simulations were performed to investigate the origins of the leakage current in UFETs.