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Title Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-through Current-based Local Thermal Annealing
Authors (Dong-Woo Cha) ; (Jun-Young Park)
DOI https://doi.org/10.5573/JSTS.2021.21.3.222
Page pp.222-228
ISSN 1598-1657
Keywords Annealing; dielectric; FinFET; hot-carrier injection (HCI); punch-through; reliability; logic transistors
Abstract Impact of device geometric structures and materials is discussed to improve power efficiency of punch-through current based electro-thermal annealing (ETA). Various sensitivities that affect device temperature during ETA are extracted and compared. Then, dielectric engineering in terms of thermal conductivity and thermal isolation is suggested for better power management. Finally, time-dependent characteristics with various thicknesses of buried dielectric layer are discussed to improve annealing speed. As a result, the contents of this paper provide a guide to better application of ETA.