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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2026-10 (Vol.26 No.05)
  4. 10.5573/JSTS.2026.26.5.384
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REFERENCES

1 
Y. Kwon, H. Park, Y. Choi, J. Sim, J. Choi, S. Park, and C. Kim, “A 15 Gb/s non-return-to-zero transmitter with 1-tap pre-emphasis feed-forward equalizer for low-power ground terminated memory interfaces”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 6, pp. 2737-2741, 2022.DOI
2 
Y. Choi, H. Park, J. Choi, J. Sim, Y. Kwon, S. Park, S. Kim, C. Sim, and C. Kim, “A 25-Gb/s single-ended PAM-4 receiver with time-windowed LSB decoder for high-speed memory interfaces”, IEEE Journal of Solid-State Circuits, vol. 58, no. 7, pp. 2005-2015, 2023.DOI
3 
Y. Kwon, H. Park, Y. Choi, J. Sim, J. Choi, S. Park, K. M. Kim, C. Choi, H. K. Jung, and C. Kim, “A 33-Gb/s/pin 1.09-pJ/bit single-ended PAM-3 transceiver with ground-referenced signaling and time-domain decision technique for multi-chip module memory interfaces”, IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2314-2325, 2023.DOI
4 
C. Han, K.-S. Lee, and J.-H. Chae, “25.2-Gb/s/pin NRZ/PAM-3 dual-mode transmitter with embedded partial DBI: Improving I/O bandwidth/pin and DBI efficiencies”, IEEE Journal of Solid-State Circuits, vol. 60, no. 5, pp. 1782-1792, 2025.DOI
5 
H. Park, J. Song, J. Sim, Y. Choi, J. Choi, J. Yoo, and C. Kim, “30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links”, IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 581-590, 2021.DOI
6 
Y. Choi, C. Sim, J. Choi, J. Sim, H. Park, Y. Kwon, S. Park, S. Kim, and C. Kim, “A 25-Gb/s single-ended PAM-4 transmitter with iPWM-based FFE and RLM-matched voltage-mode driver for high-speed memory interfaces”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 12, pp. 6375-6384, 2024.DOI
7 
J.-H. Chae, Y.-U. Jeong, and S. Kim, “Data-dependent selection of amplitude and phase equalization in a quarter-rate transmitter for memory interfaces”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 2972-2983, 2020.DOI
8 
C. Han, K.-S. Lee, J.-C. Lee, and J.-H. Chae, “A VM-terminated PAM-3 transmitter using floating middle level with enhanced signal integrity and energy efficiency for low-power memory interfaces”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 6, pp. 2653-2663, 2025.DOI
9 
S. Kim, J. Sim, Y. Choi, J. Choi, Y. Kwon, S. Park, C. Sim, J. So, T. Park, and C. Kim, “Single-ended PAM-4 transmitters with data bus inversion and ZQ calibration for high-speed memory interfaces”, IEEE Journal of Solid-State Circuits, vol. 59, no. 10, pp. 3432-3443, 2024.DOI