I. INTRODUCTION

As the demand for high-performance computation increases in fields such as artificial intelligence, cloud computing, and autonomous driving, the required data bandwidth in memory interfaces is also increasing ^[1], ^[2]. As the data rate increases, the extent of channel-induced attenuation becomes greater, leading to data distortion and more severe inter-symbol interference (ISI). To address these challenges, three-level pulse-amplitude modulation (PAM-3) has been introduced ^{[3- 5]}. However, the use of PAM signaling increases susceptibility to simultaneous switching noise (SSN) and crosstalk. For this reason, a feed-forward equalizer (FFE) is required to preserve the sensing margin reduced by distortion from channel loss and decreased voltage margin.

FFEs can be classified into voltage equalization ^{[1, 3]} and phase equalization ^{[6, 7]}. Voltage equalization employs either a discrete-tap FFE or capacitor-peaking FFE. These approaches increase the I/O capacitance (CIO) by being implemented in parallel with the output driver, which can significantly degrade the achievable I/O bandwidth under a limited power budget. Especially in the case of capacitor peaking, as the data rate increases, half-rate or quad-rate architectures are commonly adopted. However, when capacitor peaking is employed, multiple peaking capacitors are required to match the timing phases, thereby increasing the load on the output driver and further degrading the output bandwidth ^[3].

To overcome this problem, research on phase equalization has also been actively conducted. Phase equalization minimizes CIO and reduces power consumption, since the main data is pre-distorted and fed into the output driver ^{[6, 7]}. However, while voltage equalization compensates for both voltage and timing, phase equalization only compensates for timing, so the amount of channel loss it can compensate for is restricted. Therefore, this paper proposes a switched-capacitor peaking (SCP) transmitter, which, like phase emphasis, minimizes CIO while enabling compensation for larger channel loss.

This paper is organized as follows. Section II describes the overall architecture of the proposed SCP transmitter. Section III presents the concept and detailed operation of the proposed PAM-3 SCP transmitter. Section IV provides the simulation results of the proposed SCP transmitter in a 28-nm CMOS, and Section V concludes this paper.

II. PROPOSED TRANSMITTER TOP BLOCK DIAGRAM

Fig. 1 shows the top-level block diagram of the proposed SCP TX. The proposed architecture includes a 48-bit pseudo-random binary sequence (PRBS) generator for testing, a 48-to-3 serializer that converts 48 parallel data streams into 3 serial data streams, and a 3-bit/2UI encoder that maps the data into the PAM-3 format. In the PAM-3 encoding, the high–high pattern, which has the highest power consumption, is excluded ^[5]. The 8 GHz external clock enters through an AC buffer and is divided for use by the PRBS generator and the serializer. It is also used for retiming the encoder output data. Transition information is obtained by delaying $\text{H}_{\text{EVEN}}$ and $\text{L}_{\text{EVEN}}$ by 1 UI using flip-flops and comparing the previous data with the current data. The transition detector generates emphasis-enable signals according to the detected transitions. These signals control the pulsers and the switches. Capacitor peaking is generated by the pulsers using the peaking capacitors, while the switches selectively connect or disconnect the capacitors. In addition, the emphasis coefficient is adjusted using the pulser. For half-rate operation, a 2-to-1 MUX is used, and four pulsers and peaking capacitors are used, one for each rising transition and falling transition in the even and odd phases. To improve power efficiency, the output driver adopts a low-voltage swing terminated logic (LVSTL) structure, and VDDQ is set to 0.6 V.

Fig. 1. Top block diagram of the proposed transmitter.

Fig. 2 illustrates the transition levels of PAM-3 signaling, consisting of 1-level and 2-level transitions. Since the amount of channel attenuation varies depending on the transition level, the emphasis coefficient also needs to be adjusted accordingly. In the proposed SCP transmitter, the pulser and transition detector are used to control the emphasis coefficient, and the pulse width for capacitor peaking is varied based on the transition level. Because the channel loss is larger in a 2-level transition than in a 1-level transition, a higher emphasis coefficient is required to compensate for the increased attenuation. Since the channel can be modeled as an RC network, the amount of compensation can be controlled by adjusting the pulse width. A wider pulse width provides a longer compensation duration, thereby compensating for higher attenuation. Therefore, in the proposed SCP transmitter, a pulse width of $\Delta T\text{-UI}$ is applied for 1-level transitions, whereas a pulse width of $2\Delta T\text{-UI}$ is applied for 2-level transitions to perform emphasis.

Fig. 2. Transition levels of PAM-3 signaling.

III. PROPOSED SWITCHED CAPACITOR PEAKING TRANSMITTER

1. Transition Detector

The transition detector determines whether a transition occurs between consecutive input data patterns. It detects the transition by comparing the even and odd data. The detected rising and falling transition information is delivered to the pulser through an enable signal “Tran.Info”. In addition to detecting the occurrence of a transition, it also identifies the transition level and delivers it to the pulser through an enable signal “Tran.Level”, which is then used to determine the emphasis coefficient according to the PAM-3 signaling levels.

After the transition level is identified, the pulser determines the pulse width of its output. The structure of the pulser is shown in Fig. 4, and the pulse width is adjusted through delay control to set the emphasis coefficient. One UI corresponds to 62.5 ps, and the delay can be tuned from 20 ps to 43 ps. Depending on the transition level, the output is selected through a MUX, and in the case of a 2-level transition, a wider pulse is generated. For a 2-level transition, the emphasis coefficient becomes approximately twice that of a 1-level transition.

Fig. 3. Simulated voltage margin to pulser control bit.

Fig. 4. Architecture of pulser.

In PAM signaling, the amplitude levels include an intermediate level in addition to HIGH and LOW. Consequently, both under-equalization and over-equalization reduce the eye-opening. Under-equalization insufficiently compensates channel attenuation, whereas over-equalization distorts the intermediate level and closes the eyes corresponding to HIGH and LOW. Therefore, accurate adjustment of the emphasis coefficient is required.

In this work, as shown in Fig. 3, the emphasis coefficient is adjusted by tuning the pulser delay, and a digital control code of 0011 is applied to maximize the eye-sensing margin at the SS corner. By adjusting the control bits, the variation across process corners can be compensated. The SCP transmitter is verified under –9.2 dB channel loss at an 8 GHz Nyquist frequency in post-layout simulation.

When multiple discrete taps or conventional capacitor peaking are used, the emphasis coefficient is determined within the output driver. In contrast, in the proposed SCP transmitter, the emphasis coefficient is set in advance in the pulser before the output driver, as in phase emphasis. This minimizes the output driver power and CIO compared to a discrete tap FFE or a capacitor-peaking FFE. In addition, because the proposed method is based on a capacitor-peaking FFE, the CIO is minimized as in phase emphasis, but the emphasis is performed in the voltage domain, allowing compensation for higher channel loss than phase emphasis.

2. Proposed Switched Capacitor Peaking

Fig. 5 illustrates the operation of the proposed SCP transmitter. In this architecture, the transition detector operates according to the input data patterns, controlling the switch between the peaking capacitor and the output driver.

Fig. 5. Operation of proposed SCP. (a) CID pattern, (b) Transition pattern.

For CID patterns, the switch is turned off, disconnecting the peaking capacitor from the output driver, as illustrated in Fig. 5(a). This minimizes the output driver CIO, preventing bandwidth reduction and increased power consumption. Conversely, as shown in Fig. 5(b), when a transition pattern occurs, the switch is turned on, connecting the peaking capacitor to the output driver. The connected peaking capacitor provides peaking with a predetermined pulse width according to the transition level, thereby emphasizing the output data of the driver. In addition, because the capacitor is connected only during transition patterns, the settling caused by the capacitor can be prevented. As a result, the proposed SCP transmitter allows the output data to be determined exclusively by the output driver in CID patterns.

Fig. 6. Capacitor peaking simulation results according to the capacitor size. (a) peaking capacitor = 300 fF, (b) peaking capacitor = 10 pF.

Capacitor peaking FFE exploits the characteristic that the voltage difference across a capacitor cannot change instantaneously. However, in conventional capacitor-peaking methods, the RC time constant $\tau$ causes the main data to fluctuate. When a small capacitor is used to minimize CIO, the voltage changes due to peaking as shown in Fig. 6(a). Because the capacitor stores only a small amount of charge, the voltage quickly changes. As a result, during the next peaking event, the main data level is instantaneously increased by approximately 422 mV, and approximately 1.5 UI is required for settling. To prevent this, a larger capacitor can be used as shown in Fig. 6(b). However, due to the larger $\tau$, the settling time becomes longer, and approximately 110 mV of residual offset remains even after about 2 UI, including about 30 mV of DC offset.

In contrast, in the proposed SCP transmitter, only the peaking operation is applied through the capacitor, and then the switch disconnects the capacitor from the output driver. Therefore, regardless of the capacitor size, the output data level is determined solely by the output driver. In this work, a 150 fF capacitor is used for the peaking operation.

IV. SIMULATION RESULTS

Fig. 7(a) and Fig. 7(b) illustrate the layout and the power distribution, respectively. For the post-layout simulation, a channel with characteristics of -9.2 dB @ 8 GHz, as shown in Fig. 7(c), was used. With a 1 V main supply and a 0.6 V driver supply, the proposed TX consumes 27.96 mW at 24 Gb/s, corresponding to an energy efficiency of 0.129 pJ/b/dB. Fig. 8 presents the eye diagram results under different conditions. In Fig. 8(a), the conventional capacitor peaking was applied using the same capacitor value and power as the SCP transmitter, where the peaking capacitor is always connected to the output driver without switch control. Since a small capacitor is used, CM fluctuates, and the eye closes. Similarly, Fig. 8(b) shows that without emphasis, the eye also closes. In Fig. 8(c), compensation was applied only for 1-level transitions in the PAM-3 signal, which resulted in a vertical eye margin of 34 mV and a horizontal margin of 38 ps. Because the coefficients for the 2-level and 1-level transitions are set to the same value, the 2-level transitions do not receive adequate compensation, and thus, the sensing margin is not sufficiently secured. Finally, Fig. 8(d) shows the result when compensation for 2-level transitions was added, leading to improved margins of 61 mV vertically and 41 ps horizontally. With the application of transition-level dependent emphasis coefficients, the voltage margin was improved to about twice that of Fig. 8(c). Table 1 summarizes and compares the proposed structure with recently reported memory interfaces. In ^[4], de-emphasis compensates for only 4.4 dB of channel loss. In ^[5], channel attenuation cannot be compensated because no equalizer is used. In ^[6], phase equalization is used to minimize CIO, but the compensated channel loss is limited to 2.76 dB. Although ^[8] achieves higher channel-loss compensation, it requires two supply voltages for pre-emphasis. In ^[9], the emphasis coefficient is also adjusted according to the transition level in PAM signaling. However, since the control is implemented at the output driver, it results in an increase in CIO. In contrast, the proposed SCP transmitter minimizes CIO and achieves pre-emphasis without requiring an additional supply voltage.

Fig. 7. (a) Layout of proposed transmitter, (b) Power breakdown, (c) Channel attenuation.

Fig. 8. Simulation PAM-3 eye diagrams of the transmitter. (a) w/o switch, (b) w/o emphasis, (c) w/o transition level adaptation, (d) w/ transition level adaptation.

V. CONCLUSION

This work presents an SCP transmitter for high-speed memory interfaces to compensate for channel-induced attenuation while minimizing CIO. The emphasis coefficient is predetermined before the output driver, enabling FFE operation while minimizing the overhead of the output driver. By applying pre-emphasis using transition-level detection and controlling the peaking capacitor, the proposed SCP transmitter achieves effective loss compensation without increasing the driver capacitance or inducing common-mode voltage fluctuations. Post-layout simulations in a 28-nm CMOS process demonstrate operation at 24 Gb/s over a channel with -9.2 dB of loss at 8 GHz, achieving an energy efficiency of 0.129 pJ/b/dB and eye margins of 61 mV vertically and 0.65 UI horizontally.