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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2026-06 (Vol.26 No.03)
  4. 10.5573/JSTS.2026.26.3.212
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REFERENCES

1 
M. Rostami, F. Koushanfar, R. Karri, 2014, A primer on hardware security: Models, methods, and metrics, Proceedings of the IEEE, Vol. 102, No. 8, pp. 1283-1295DOI
2 
U. Guin, K. Huang, D. DiMase, J. M. Carulli, M. Tehranipoor, Y. Makris, 2014, Counterfeit integrated circuits: A rising threat in the global semiconductor supply chain, Proceedings of the IEEE, Vol. 102, No. 8, pp. 1207-1228DOI
3 
A. Chakraborty, N. G. Jayasankaran, Y. Liu, J. Rajendran, O. Sinanoglu, A. Srivastava, Y. Xie, M. Yasin, M. Zuzak, 2019, Keynote: A disquisition on logic locking, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, No. 10, pp. 1952-1972DOI
4 
P. Subramanyan, S. Ray, S. Malik, 2015, Evaluating the security of logic encryption algorithms, Proc. of 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137-143DOI
5 
J. A. Roy, F. Koushanfar, I. L. Markov, 2008, EPIC: Ending piracy of integrated circuits, Proc. of the Conference on Design, Automation and Test in Europe, pp. 1069-1074DOI
6 
J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, 2012, Security analysis of logic obfuscation, Proc. of the 49th Annual Design Automation Conference, pp. 83-89DOI
7 
J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, R. Karri, 2013, Fault analysis-based logic encryption, IEEE Transactions on Computers, Vol. 64, No. 2, pp. 410-424DOI
8 
J. B. Wendt, M. Potkonjak, 2014, Hardware obfuscation using PUF-based logic, Proc. of 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 270-271DOI
9 
Y. W. Lee, N. A. Touba, 2015, Improving logic obfuscation via logic cone analysis, Proc. of 2015 16th Latin-American Test Symposium (LATS)DOI
10 
S. Khaleghi, K. Da Zhao, W. Rao, 2015, IC piracy prevention via design withholding and entanglement, Proc. of The 20th Asia and South Pacific Design Automation Conference, pp. 821-826DOI
11 
A. Baumgarten, A. Tyagi, J. Zambreno, 2010, Preventing IC piracy using reconfigurable logic barriers, IEEE Design & Test of Computers, Vol. 27, No. 1, pp. 66-75DOI
12 
M. Yasin, B. Mazumdar, J. J. V. Rajendran, O. Sinanoglu, 2016, SARLock: SAT attack resistant logic locking, Proc. of 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 236-241DOI
13 
Y. Xie, A. Srivastava, 2018, Anti-SAT: Mitigating SAT attack on logic locking, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 2, pp. 199-207DOI
14 
M. Yasin, B. Mazumdar, O. Sinanoglu, J. Rajendran, 2017, Removal attacks on logic locking and camouflaging techniques, IEEE Transactions on Emerging Topics in Computing, Vol. 8, No. 2, pp. 517-532DOI
15 
K. Shamsi, T. Meade, M. Li, D. Z. Pan, Y. Jin, 2018, On the approximation resiliency of logic locking and IC camouflaging schemes, IEEE Transactions on Information Forensics and Security, Vol. 14, No. 2, pp. 347-359DOI
16 
J. Zhou, X. Zhang, 2021, Generalized SAT-attack-resistant logic locking, IEEE Transactions on Information Forensics and Security, Vol. 16, pp. 2581-2592DOI
17 
Y. Liu, M. Zuzak, Y. Xie, A. Chakraborty, A. Srivastava, 2020, Strong anti-SAT: Secure and effective logic locking, Proc. of 2020 21st International Symposium on Quality Electronic Design (ISQED), pp. 199-205DOI
18 
M. Yasin, B. Mazumdar, J. J. V. Rajendran, O. Sinanoglu, 2017, TTLock: Tenacious and traceless logic locking, Proc. of 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 166-166DOI
19 
M. Yasin, A. Sengupta, M. T. Nabeel, M. Ashraf, J. Rajendran, O. Sinanoglu, 2017, Provably-secure logic locking: From theory to practice, Proc. of the 2017 ACM SIGSAC Conference on Computer and Communications Security, pp. 1601-1618DOI
20 
Z. Han, M. Yasin, J. J. V. Rajendran, 2020, Multi-objective strategies for stripped-functionality logic locking, Proc. of 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5DOI