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References

1 
X. Tang, Y. Zhao, L. Wang, and H. Chen, ``Low-power SAR ADC design: overview and survey of state-of-the-art techniques,'' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 6, pp. 2249--2262, Jun. 2022.DOI
2 
J. A. Fredenburg and M. P. Flynn, ``A 90-MS/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC,'' IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2898--2904, Dec. 2012.DOI
3 
R. T. Baird and T. S. Fiez, ``Linearity enhancement of multibit $\Delta\Sigma$ A/D and D/A converters using data-weighted averaging,'' IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 12, pp. 753--762, Dec. 1995.DOI
4 
Y. Lu, X. Tang, L. Wang, and H. Chen, ``An overview of noise-shaping SAR ADC: From fundamentals to the frontier,'' IEEE Open Journal of Circuits and Systems, vol. 2, pp. 775--788, Dec. 2021.DOI
5 
Y. Song, C.-H. Chan, Y. Zhu, L. Geng, S.-P. U., and R. P. Martins, ``Passive noise shaping in SAR ADC with improved efficiency,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 2, pp. 416--420, Feb. 2018.DOI
6 
H. Zhuang, Y. Zhu, S.-W. Sin, U. F. Chou, and R. P. Martins, ``A second-order noise-shaping SAR ADC with passive integrator and tri-level voting,'' IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1636--1647, Jun. 2019.DOI
7 
C.-C. Liu and M.-C. Huang, ``A 0.46 mW 5 MHz-bandwidth 79.7 dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter,'' in Proceedings of the 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 466--467, Feb. 2017.DOI
8 
Y. Zhang, S. Liu, B. Tian, Y. Zhu, C.-H. Chan, and Z. Zhu, ``A second-order noise-shaping SAR ADC with lossless dynamic-amplifier-assisted integrator,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 10, pp. 1819--1823, Oct. 2020.DOI
9 
J. Lin, M. Miyahara, and A. Matsuzawa, ``A 15.5 dB wide-signal-swing dynamic amplifier using a common-mode voltage detection technique,'' in Proceedings of the 2011 IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, pp. 21--24, May 2011.DOI
10 
R. G. Carvajal, J. Ramírez-Angulo, A. J. López-Martín, C. C. Enz, A. Torralba, J. Galán, and F. Muñoz, ``The flipped voltage follower: a useful cell for low-voltage low-power circuit design,'' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1276--1291, Jul. 2005.DOI
11 
M. Neitola and T. Rahkonen, ``A generalized data-weighted averaging algorithm,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 2, pp. 115--119, Feb. 2010.DOI
12 
Y.-S. Shu, L.-T. Kuo, and T.-Y. Lo, ``An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz bandwidth in 55 nm CMOS,'' IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928--2940, Dec. 2016.DOI
13 
W. Jiang, Y. Zhu, M. Zhang, C.-H. Chan, and R. P. Martins, ``A temperature-stabilized single-channel 1 GS/s 60 dB-SNDR SAR-assisted pipelined ADC with dynamic $G_m$-$R$-based amplifier,'' IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 322--332, Feb. 2020.DOI
14 
D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, ``A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time,'' in Proceedings of the 2007 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, pp. 314--315, Feb. 2007.DOI
15 
L. Jie, B. Zheng, and M. P. Flynn, ``A calibration-free time-interleaved fourth-order noise-shaping SAR ADC,'' IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3386--3395, Dec. 2019.DOI
16 
H. Zhuang, J. Liu, H. Tang, X. Peng, and N. Sun, ``A fully dynamic low-power wideband time-interleaved noise-shaping SAR ADC,'' IEEE Journal of Solid-State Circuits, vol. 56, no. 9, pp. 2680--2690, Sep. 2021.DOI
17 
H.-J. Kim, J.-H. Boo, K.-I. Cho, Y.-S. Kwak, and G.-C. Ahn, ``A single-loop third-order 10 MHz-bandwidth source-follower-integrator-based discrete-time delta-sigma ADC,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 2, pp. 401--405, Feb. 2023.DOI