1. Shared Amplifier for Lossless SC Integration

Fig. 2 shows the second-order integrator with ping-pong SC structures used in ^[8] and in the proposed work, along with the same timing diagram used in both. As shown in Fig. 2(a), the first integrator in ^[8] consists of C${}_{\rm INT1A}$, C${}_{\rm INT1B}$, and Amp1, an amplifier with a gain of two. The second integrator is composed of C${}_{\rm INT2A}$, C${}_{\rm INT2B}$, and Amp2, which provides a gain of three. In this structure, two individual amplifiers are used to generate V${}_{\rm INT1}$ and V${}_{\rm INT2}$ through separate integration paths, followed by signal summation via a multi-path comparator ^[2]. The proposed ADC shown in Fig. 2(b) employs a shared amplifier to realize the second-order integrator. The fully-differential flipped voltage follower (FD-FVF), introduced in ^[10], eliminates the need for reset operations between consecutive amplification phases. This enables amplifier sharing between two integrators, resulting in area reduction.

The timing diagrams for both ^[8] and the proposed architecture are shown in Fig. 2(c). After the residue voltage sampling phase $\Phi_{R}$${}_{\rm S}$, a charge sharing occurs between the C${}_{\rm DAC}$ and C${}_{\rm INT1A}$ during $\Phi_{1}$. In $\Phi_{2}$, compensation and charge sharing are simultaneously carried out by the first and second integrators, respectively. Then, during $\Phi_{3}$, the second integrator performs compensation. Although the integrators in ^[8] and the proposed ADC operate with the same timing diagram, they differ in amplifier configuration. In ^[8], separate amplifiers (Amp1 and Amp2) are used for integration: Amp1 operates in $\Phi_{2}$, while Amp2 operates in $\Phi_{3}$. In contrast, the proposed design uses a single amplifier (Amp3) for integration, which is shared between $\Phi_{2}$ and $\Phi_{3}$.

Fig. 2. Schematic of the second-order integrator with (a) from ^[8], (b) the proposed design, and (c) the timing diagram.

2. Realization of an Ideal Second-Order NS

Fig. 3 illustrates the circuit-level operation of the lossless integrator. The C${}_{\rm DAC}$ and integration capacitors C${}_{\rm INT1A/B}$ and C${}_{\rm INT2A/B}$ are designed to have equal capacitance to achieve an ideal second-order NTF. The integration process begins after SAR conversions are completed. The residue voltage of $N${th} cycle V${}_{\rm RES}$(N) remains on the C${}_{\rm DAC}$, while capacitors C${}_{\rm INT1A}$ and C${}_{\rm INT2A}$ hold the integration voltages of the $(N-1)${th} cycle, V${}_{\rm INT1} (N-1)$ and V${}_{\rm INT2} (N-1)$, respectively.

Fig. 3. Circuit-level operation of the lossless integrator.

During $\Phi_{1}$, in the first integrator, the charge on the C${}_{\rm DAC}$ is shared with capacitor C${}_{\rm INT1A}$, generating the first intermediate voltage V${}_{\rm INT1^{'}} (N)$, expressed following as Eqs. (1) and (2):

In $\Phi_{2}$, V${}_{\rm INT1^{'}} (N)$ is amplified by a factor of two through the amplifier then sampled on capacitor C${}_{\rm INT1B}$. As a result, V${}_{\rm INT1} (N)$ accumulates both V${}_{\rm RES} (N)$ and V${}_{\rm INT1} (N-1)$, without any loss as

Transforming Eq. (3) into the z-domain gives the following equation

In the operation of the second integrator, the second integrator remains idle while the first integrator performs integration in $\Phi_{1}$, during which the C${}_{\rm DAC}$ holds V${}_{\rm INT1^{'}}(N)$.

During $\Phi_{2}$ for integration, charge sharing with C${}_{\rm DAC}$ {}and C${}_{\rm INT2A}$ produces the second intermediate voltage V${}_{\rm INT2^{'}} (N)$, expressed as Eqs. (5) and (6):

Subsequently, during $\Phi_{3}$, compensation occurs in the second integrator. As a result, V${}_{\rm INT2}(N)$ becomes

Unlike V${}_{\rm INT1}$(N) in Eq (3), Eq (7) shows that the integration voltage V${}_{\rm INT2}$(N) is attenuated by a factor of two, even after compensation.

Fig. 4. Signal flow of the proposed second-order NS-SAR ADC.

Fig. 4 presents the signal flow of the proposed second-order NS-SAR ADC, illustrating the attenuation and gain factors denoted as (a)-(e). In the first integrator, although charge sharing between the C${}_{\rm DAC}$ and C${}_{\rm INT1A/B}$ causes voltage attenuation, compensation enables lossless integration. However, in the second integrator, the loss caused by charge sharing between the C${}_{\rm DAC}$ and C${}_{\rm INT2A/B}$ is not fully compensated, despite the compensation being applied in the same manner as in the first integrator. To achieve an ideal second-order integration, a gain of two compensation is applied to V${}_{\rm INT2}$ by designing the comparator input paths to have specific relative gain as follows:

The corresponding z-domain expression is given in

The multi-path comparator combines V${}_{\rm INT1}$(z), V${}_{\rm INT2}$(z), and V${}_{\rm IN}$(z) --- the input voltage sampled on the C${}_{\rm DAC}$ --- with the quantization error Q(z) to generate D${}_{\rm OUT}$(z) as follows:

1. Proposed NS SAR ADC

Fig. 5 illustrates the schematic and timing diagram of the proposed ADC. The proposed NS-SAR ADC consists of a coarse SAR ADC, a 4-bit dynamic weight averaging (DWA) logic ^[11], and fine SAR ADC with loop filter. In the proposed NS-SAR ADC, capacitor mismatch in the C${}_{\rm DAC}$ is dominant in the most significant bit (MSB) region, which significantly affects linearity ^[12]; therefore, DWA is applied only to the 4 MSBs considering the target resolution and logic complexity. The fine SAR ADC consists of a C${}_{\rm DAC}$, a loop filter, a multi-path comparator, and SAR logic. It performs a 6-bit conversion, including one redundant bit that covers 16 LSBs to mitigate the effect of comparator offset mismatch between the coarse and fine SAR ADCs. The multi-path comparator in the fine SAR ADC sums the C${}_{\rm DAC}$ residual voltage V${}_{\rm RES}$ with the integrated signals V${}_{\rm INT1}$ and V${}_{\rm INT2}$, with relative gains of 1, 1, and 2, respectively, as in ^[6].

In the $N${th} cycle of the timing diagram in Fig. 5, the proposed SAR ADC operates as follows. During the sampling phase $\Phi_{\rm S}$, the input signal is sampled through a bootstrapped switch shared by both the coarse and fine SAR ADCs. During four $\Phi_{C1}$ phases, the coarse SAR ADC performs a 4-bit asynchronous conversion. In phase $\Phi_{D}$, the DWA logic operates based on the coarse SAR ADC outputs to generate a 15-bit thermometer code that switches fifteen 16C${}_{U}$ segments in the C${}_{\rm DAC}$ array of the fine SAR ADC. Following that, during six $\Phi_{C2}$ phases, the comparator of the fine SAR ADC operates asynchronously, and its output is processed by the SAR logic to control the C${}_{\rm DAC}$, thereby obtaining a 6-bit digital code. In $\Phi_{1}$, charge sharing between the C${}_{\rm DAC}$ and C${}_{\rm INT1A}$ generates the first intermediate voltage, as described in Eq. (2). In $\Phi_{2}$, the first intermediate voltage is compensated and then sampled onto C${}_{\rm INT1B}$ as V${}_{\rm INT1}$, representing the first integration voltage. Simultaneously, in $\Phi_{2}$, charge sharing between the C${}_{\rm DAC}$ and C${}_{\rm INT2A}$ in the second integrator produces the second intermediate voltage, as shown in Eq (6), which is then compensated in $\Phi_{3}$ and sampled onto C${}_{\rm INT2B}$ as V${}_{\rm INT2}$.

Subsequently, in the $(N+1)${th} cycle, following the sampling phase $\Phi_{\rm S}$, four $\Phi_{C1}$ phases and $\Phi_{D}$ proceed sequentially in the same manner as in the N${}^{th}$ cycle. $\Phi_{4}$ stays high from the falling edge of $\Phi_{\rm S}$ to the falling edge of the sixth $\Phi_{C2}$, which corresponds to the end of the fine SAR conversion. During this period, the voltage on the C${}_{\rm DAC}$ top plate, along with V${}_{\rm INT1}$ and V${}_{\rm INT2}$, is fed into the multi-path comparator. During the subsequent phases $\Phi_{5}$-$\Phi_{7}$, C${}_{\rm INT1A}$, and C${}_{\rm INT2A}$ are configured as a second-order integrator to generate V${}_{\rm INT1}$ and V${}_{\rm INT2}$, respectively, unlike in the N${}^{th}$ cycle where C${}_{\rm INT1B}$ and C${}_{\rm INT2B}$ are used.

To ensure consistent gain between the first and second integrators, all internal nodes of the amplifier must be sufficiently settled before operation begins. Without proper settling, the amplifier may exhibit different gain characteristics during $\Phi_{2}$ and $\Phi_{6}$ (for the first integrator) and $\Phi_{3}$ and $\Phi_{7}$ (for the second integrator), which are responsible for compensation. Such gain mismatch may degrade integration accuracy and overall linearity. To address this, $\Phi_{A}$ is activated early at the rising edges of $\Phi_{1}$ and $\Phi_{5}$, allowing sufficient settling time. The amplifier is then turned off at the falling edges of $\Phi_{3}$ and $\Phi_{7}$ after integration completes. Compared to the use of dedicated amplifiers, which require their own early turn-on for each, the proposed shared amplifier operates with about 25% reduced power consumption for integrations.

Fig. 5. Schematic and timing diagram of the proposed NS-SAR ADC.

2. Fully-differential Flipped Voltage Follower

Fig. 6(a) shows the schematic of the FD-FVF, modified from ^[13], which is employed in the loop filter. To reduce static power consumption by enabling dynamic operation, S${}_{\rm R1}$ and S${}_{\rm R2}$ switches, which are driven by the amplifier clock signal $\Phi_{\rm A}$, are employed. The reset-free operation of the FD-FVF amplifier enables its sharing between the first and second integrators. In the dynamic amplifier scheme ^[9], the gain depends on the amplification time. In contrast, the FD-FVF provides a gain set by its transconductance and output resistance, as long as all internal nodes are fully settled, which mitigates the impact of clock jitter ^[13]. The linearity of amplifier is enhanced by shunt--shunt feedback networks formed by transistors M1, M3, M5 and M2, M4, M6, which stabilize the gate--source voltages of the input pair.

Fig. 6(b) shows the simulated gain variation across PVT conditions, where $-40^\circ$C and $85^\circ$C correspond to the cold and hot corners, respectively. Across all process corners and under $\pm 10$% supply variations, the Signal-to-Quantization-Noise Ratio (SQNR) variation remains within $-1.3$ dB, which has a negligible impact on the ADC performance.

Fig. 6. Schematic of the FD-FVF (a) and simulated gain against power supply and process corner variations (b).

3. Multi-path Comparator

As shown in Fig. 7, a multi-path comparator modified from ^[6] and ^[14] is used in the NS-SAR ADC to perform voltage summation. The input transistors(M13-M18) and the switches(M1-M3) connected to their sources are sized with specific ratio to enable voltage summation at T${}_{\rm P}$ and T${}_{\rm N}$ with relative gain, as in ^[6]. Intermediate transistors M6 and M9 provide electrical isolation between the input and latching stages, effectively mitigating kickback noise ^[14].

Fig. 7. Schematic of the multi-path comparator.

During the reset phase ($\Phi_{\rm C} =$ low), the T${}_{\rm P}$ and T${}_{\rm N}$ nodes are pre-charged to V${}_{\rm DD}$. Meanwhile, M6 and M9 discharge the output nodes OUT${}_{\rm P}$ and OUT${}_{\rm N}$ to ground. When $\Phi_{\rm C}$ transitions to high, transistors M1-M3, and M12 are enabled while M4 and M5 are turned off. Subsequently, the input transistors M13, M15, and M17---connected to V${}_{\rm RESP}$, V${}_{\rm INT1P}$, and V${}_{\rm INT2P}$, respectively---discharge the T${}_{\rm P}$ node with currents proportional to their sizing ratios, applying gain to each input. Similarly, M14, M16, and M18---connected to V${}_{RESN}$, V${}_{\rm INT1N}$, and V${}_{\rm INT2N}$---discharge the T${}_{\rm N}$ node. As T${}_{P}$ and T${}_{\rm N}$ are discharged, M7 and M8 can no longer clamp the comparator outputs OUT${}_{\rm P}$ and OUT${}_{\rm N}$ to ground, enabling the back-to-back inverter pair formed by M7--M11 to latch decision as described in ^[14].