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References

1 
K. Tomioka, T. Yasue, R. Funatsu, and T. Wada, ``Improved correlated multiple sampling by using interleaved pixel source follower for high-resolution and high-frame-rate CMOS image sensor,'' IEEE Transactions on Electron Devices, vol. 68, no. 5, pp. 2326--2334, May 2021.DOI
2 
W. Deng and E. R. Fossum, ``Deep sub-electron read noise in image sensors using a multigate source follower,'' IEEE Transactions on Electron Devices, vol. 69, no. 6, pp. 2986--2991, Jun. 2022.DOI
3 
H. Kim, S. Lee, J. Park, and K. Cho, ``A 0.64 µm 4-photodiode 1.28 µm 50-megapixel CMOS image sensor with 0.98 e$^-$ temporal noise and 20 Ke$^-$ full-well capacity employing quarter-ring source follower,'' in Proc. of the IEEE International Solid-State Circuits Conference (ISSCC), pp. 96--97, Feb. 2023.URL
4 
A. Boukhayma, A. Kraxner, A. Caizzone, M. Yang, D. Bold, and C. Enz, ``Comparison of two in-pixel source follower schemes for deep sub-electron noise CMOS image sensors,'' IEEE Journal of the Electron Devices Society, vol. 10, pp. 687--695, May 2022.DOI
5 
J. H. Kim, S. C. Kim, and J. Lee, ``Atomistic analysis on random telegraph noise of source-follower transistors in sub-micrometer CMOS image sensor pixels,'' in Proc. of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 24--27, Sep. 2024.DOI
6 
H. Lee and I. Yun, ``TFET-based pixel source follower of CMOS image sensor for improved linearity and high signal-to-noise ratio,'' IEEE Sensors Journal, vol. 23, no. 17, pp. 19239--19244, Sep. 2023.DOI
7 
K. Y. Kim, H. Kim, M. Choi, K. Oh, H. Yoo, Y. Kim, Y. Sol, S. Park, J.-K. Lee, and C.-K. Baek, ``New tunneling source follower with low 1/f noise and high voltage gain,'' Scientific Reports, vol. 14, no. 1, Jan. 2024.DOI
8 
H. K. Phulawariya, R. Chaudhary, S. Tiwari, and R. Saha, ``Realization of logic performance using double-gate TFET (DG-TFET) and Ge-source DG-TFET (s-Ge-TFET),'' in Proc. of the 2023 3rd International Conference on Artificial Intelligence and Signal Processing (AISP), pp. 1--5, Mar. 2023.DOI
9 
P. Shukla, M. Khosla, N. Sood, and T. Chawla, ``Design and comparison analysis of Ge-source hetero-stacked L-shape TFET with homostacked L-shape TFET,'' in Proc. of the 2022 2nd International Conference on Intelligent Technologies (CONIT), pp. 1--6, Jun. 2022.DOI
10 
A. Anam, S. I. Amin, and D. Prasad, ``Simulation study and comparative analysis of proposed novel hybrid DG-TFET with conventional TFET structures for improved performance,'' in Proc. of the 2021 IEEE International Symposium on Smart Electronic Systems (iSES), pp. 311--315, Dec. 2021.DOI
11 
P. Singh, D. P. Samajdar, and D. S. Yadav, ``A low-power single-gate L-shaped TFET for high-frequency application,'' in Proc. of the 2021 6th International Conference for Convergence in Technology (I2CT), pp. 1--6, Apr. 2021.DOI
12 
R. Paul, ``Performance investigation and optimization of 2-D material-based double-gate tunneling field-effect transistor (DG-TFET),'' in Proc. of the International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE), pp. 1--4, Nov. 2022.DOI
13 
S. Yadav, M. Singh, T. Chaudhary, and B. Raj, ``Design of vertical double-source TFET for low-power applications,'' in Proc. of the International Conference on Electronics, Communication and Signal Processing (ICECSP), pp. 8--10, Jan. 2024.DOI
14 
P. Dhiman, K. K. Kavi, R. K. Ratnesh, and A. Kumar, ``Controlling the ambipolar current by using graded-drain doped TFET,'' in Proc. of the 2023 International Conference on Device Intelligence, Computing and Communication Technologies (DICCT), pp. 249--252, Jul. 2023.DOI
15 
A. Jain, G. Saini, A. Mudgal, and A. Mehra, ``Comparison between hetero-junction technique TFET and conventional TFET,'' in Proc. of the 2021 International Conference on Computer Communication and Informatics (ICCCI), pp. 1--5, Jan. 2021.DOI
16 
M. K. Anvarifard and A. A. Orouji, ``Energy band adjustment in a reliable novel charge-plasma SiGe-source TFET to intensify the BTBT rate,'' IEEE Transactions on Electron Devices, vol. 68, no. 10, pp. 5284--5290, Oct. 2021.DOI
17 
S. Shailendra and B. Raj, ``Analytical and compact modeling analysis of a SiGe hetero-material vertical L-shaped TFET,'' Silicon, pp. 1--11, May 2021.DOI
18 
S. Singh and B. Raj, ``Analysis of ONOFIC technique using SiGe heterojunction double-gate vertical TFET for low-power applications,'' Silicon, pp. 1--10, Dec. 2020.DOI
19 
S.-H. Kim, J.-J. Park, J.-I. Lee, H.-W. Kim, J.-H. Kim, and B.-G. Park, ``Simulation study on optimizing tunneling field-effect transistor,'' Proc. of the Korean Institute of Electrical Engineers, pp. 49--52, Jun. 2014.URL
20 
Upasana, M. Gupta, R. Narang, and M. Saxena, ``Merits of designing tunnel field-effect transistors with underlap near drain region,'' Proc. of the Annual IEEE India Conference (INDICON), pp. 17--20, Dec. 2015.DOI
21 
P. Singh, V. Chauhan, D. Ray, and S. Dash, ``Ambipolar performance improvement of dual-material TFET using drain underlap engineering,'' in Proceedings of the IEEE Electron Devices Kolkata Conference (EDKCON), pp. 24--25, Nov. 2018.DOI
22 
S. G. Dinda, S. Sundar, and K. Iyer, ``Study of ambipolar current of a steep-slope tunneling FET with drain underlap,'' in Proceedings of the 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), pp. 1--4, Jul. 2020.DOI
23 
Synopsys, Sentaurus Device User Guide, Version K-2015.06, Synopsys, Inc., Mountain View, CA, USA, Jun. 2009.URL