I. INTRODUCTION

In recent years, CMOS image sensors (CIS) have attracted significant attention as a key technology for advanced imaging systems, enabling high-resolution image capture with low power consumption and excellent noise performance. CIS are widely used in diverse applications, including consumer electronics, automotive systems, industrial inspection, and scientific imaging, where high-speed readout and reliable analog signal processing are essential. To meet the growing demand for compact, high-performance imaging solutions, CIS technology continues to advance, offering improved speed, reduced power consumption, and enhanced signal-to-noise ratio. Fig. 1(a) shows the circuit schematic of CIS pixel and Fig. 1(b) shows its timing diagram when the correlated double sampling (CDS) is applied. The reset gate (RG) is turned on to remove the carriers from the floating diffusion (FD), which is connected to the gate of the source follower (SF). The selector transistor (SEL) is then turned on to read out the reset level through the column bus. Next, the transfer gate (TG) is activated to transfer the signal charge stored in the photodiode (PD) to the FD node. In this operation of CIS, the SF plays a crucial role as a readout buffer transistor. It converts the charge-to-voltage signal from the photodiode and delivers it to the column readout line, driving the next stage without significant signal degradation. Therefore, the voltage gain (A${}_{\rm v}$) of the SF directly affects signal integrity, especially in low-light imaging conditions. Improving the SF's gain not only enhances image quality but also helps maintain high dynamic range in miniaturized pixels. Additionally, the SF provides high input impedance, reducing the impact on subsequent stages and improving overall circuit stability. However, the push for higher resolution and cost reduction has led to a reduction in pixel size, posing challenges in maintaining the gain values of SF. To address these challenges, extensive research has been conducted to preserve SF gain ^[1-5]. Recently, studies have also explored the use of tunnel field-effect transistor (TFET) as alternatives to n-type metal-oxide-semiconductor field-effect transistors (NMOS) ^[6,7]. The A${}_{\rm v}$ is determined by the transconductance (g${}_{\rm m}$), body transconductance (g${}_{\rm mb}$), and output conductance (g${}_{\rm ds}$) as follows.

In an NMOS transistor, g${}_{\rm ds}$ is influenced by channel length modulation and drain-induced barrier lowering (DIBL) due to the drain voltage. In contrast, in a TFET, the drain current is governed by band-to-band tunneling (BTBT) between the source and the adjacent channel region. As a result, the effect of the drain voltage, such as drain-induced barrier thinning (DIBT), on g${}_{\rm ds}$ is significantly smaller than in an NMOS transistor, enabling a higher A${}_{\rm v}$. Although the TFET inherently has the disadvantage of one-way directional current flow due to its device structure and operating principle, this does not cause any issue in CIS pixel operation. This is because, in a pixel source follower, the drain is connected to supply voltage (V${}_{DD}$) and the source is connected to ground through a selector transistor, ensuring that the current always flows from drain to source during signal readout. With appropriate biasing, the tunneling condition can be reliably maintained, and therefore, the TFET-based source follower can achieve higher gain through its low g${}_{\rm ds}$ while maintaining the operational reliability of the CIS pixel.

However, as illustrated in Fig. 2 obtained by technology computer-aided design (TCAD) simulation, the scaling of gate length to 20 nm in TFETs has resulted in a significant decrease in gain values. To overcome this limitation, optimizations have been performed by adjusting critical parameters of TFETs. This paper investigates the role of the SF in CIS and discusses structural optimizations of TFETs to enhance SF characteristics. The focus is on key factors such as reducing silicon-on-insulator (SOI) thickness, introducing drain underlap, and modifying drain material properties.

Fig. 1. (a) Circuit schematic and (b) timing diagram of a CIS pixel.

Fig. 2. Gain (A$_{\rm v}$) comparison between MOSFET and TFET for gate lengths ranging from 200 nm to 20 nm.

II. TUNNELING MODEL CALIBRATION

This study was conducted using the Synopsys Sentaurus TCAD simulation tool to analyze and optimize device characteristics. In this study, a quantum-mechanical approach was adopted in this research to evaluate carrier confinement effects near the semiconductor-insulator interface. Furthermore, mobility variations due to doping levels and carrier lifetime governed by the Shockley--Read--Hall recombination were considered. The Band-to-Band Tunneling (BTBT) model was calibrated using the Sentaurus TCAD tool, and for this purpose, planar Si and SiGe TFETs were fabricated, as illustrated in Figs. 3(a) and 3(b). For the Si TFET, both SOI source implantation and drain implantation with arsenic were performed under identical process conditions. Meanwhile, the SiGe TFET was fabricated on an SOI (100) substrate, incorporating a 40 nm-thick Si$_{0.7}$Ge$_{0.3}$layer on a 60 nm-thick, lightly p-doped ($1 \times 10^{15}$ cm$^{-3}$) SOI region. To complete the device structure, a Si capping layer was deposited over the SiGe channel, followed by the formation of a 200 nm-thick poly-Si gate and a 3 nm-thick SiO$_2$ dielectric layer. The electrical characteristics of the fabricated Si and SiGe TFETs were evaluated by measuring their transfer curves at a drain voltage (V${}_{DS}$) of 1.0 V, with both devices having a gate length and width of 400 nm. The Kane BTBT model was employed to simulate the experimental results, and its parameters were calibrated accordingly (2).

Fig. 3. Cross-sectional views of (a) Si TFET and (b) SiGe TFET for calibration.

In this model, the BTBT generation rate ($G$) per unit volume was defined under the uniform electric field assumption, where $F_0 = 1$ V/m, and $P = 2.5$ was applied for indirect BTBT. The pre-factor ($A$) and exponential factor ($B$) were extracted as Kane parameters, with $F$ representing the electric field in the system. To achieve a high degree of accuracy between experimental measurements and simulation results, multiple iterative simulations were performed to fine-tune the $A$ and $B$ parameters. The optimized values were selected to ensure the best fit, as depicted in Fig. 4. The log-scale transfer characteristics confirmed a strong correlation between the simulated and measured data. From this calibration, the Si TFET's BTBT model yielded $A = 4 \times 10^{14}$ cm$^{-1}\cdot$s$^{-1}$ and $B = 9.9 \times 10^6$ V/cm. Meanwhile, for the SiGe TFET, the extracted Ge-related parameters were $A = 3.1 \times 10^{16}$ cm$^{-1}\cdot$s$^{-1}$ and $B = 7.1 \times 10^5$ V/cm.

Fig. 4. Calibrated transfer curves of Si and SiGe TFET.

III. Device Structure and A${}_{\mathbf v}$ Extraction

The basic structural parameters of the TFET used in this study are as follows. Unless otherwise specified, these parameters were employed throughout the simulations. The source, body, and drain regions were formed using SiGe with a thickness of 15 nm on top of a 50 nm-thick buried oxide (BOX) layer. The gate oxide thickness is 1 nm, and the gate length is 20 nm. The source doping concentration is p-type $10^{20}$ cm${}^{-3}$, the body doping is p-type $10^{15}$ cm${}^{-3}$, and the drain doping is n-type $10^{20}$ cm${}^{-3}$.

As mentioned in the Section I, the primary role of the SF in a CIS is to transfer the signal generated by incident light with minimal loss. Therefore, in this study, the A${}_{\rm v}$ is extracted to evaluate the performance of the SF. In the SF, A${}_{\rm v}$ is defined as the change in the output source voltage with respect to a change in the input gate voltage. Accordingly, A${}_{\rm v}$ is extracted by sweeping the gate voltage while fixing the drain current at constant value and observing the corresponding variation in the source voltage.

IV. GEMANIUM RATIO IN SIGE

Research on TFETs has been continuously conducted ^[8-15], with most studies focusing on improving the insufficient on-current. To achieve this, the TFET is fabricated using SiGe material ^[16-18], where the proportion of Ge plays a significant role in determining the on-current performance. As illustrated in Fig. 5, the on-current exhibits a noticeable dependency on the Ge composition. In the case of a transistor used as the source follower (SF) in a CIS, a high on-current is not required as in typical switching applications; however, it is still necessary to secure an adequate on-current level depending on the application. In this study, the target operating current is set to 10 ?A/?m. Based on the observation shown in Fig. 5, a Ge proportion of 50% is selected as the optimized parameter in this study to ensure sufficient on-current for proper SF operation while maintaining acceptable gain characteristics.

Fig. 5. Relationship between Ge ratio in SiGe, drain current, and gain (A$_{\rm v}$) for TFET. The plot shows that at a Ge ratio of approximately 50%, the drain current meets the required operational range, while maintaining an adequate gain value for optimized performance.

V. SOI THICKNESS

To further increase the gain of the TFET, this study explores the impact of optimizing the SOI thickness. The SOI thickness refers to the thickness of the silicon layer above the BOX layer, as illustrated in Fig. 6. This layer is situated beneath the gate, and its thickness plays a critical role in determining the electrical performance of the device ^[19]. As depicted in Fig. 7, reducing the SOI thickness improves the gain of the TFET. Due to the extremely short channel length of 20 nm, it can be observed that even with an SOI thickness of 15 nm, the influence of the drain voltage on the tunneling junction between the source and the channel cannot be sufficiently suppressed, and the highest gain is achieved when the SOI thickness is reduced to 3 nm. Based on this result, an SOI thickness of 3 nm was selected as the optimized parameter in this study. Reducing the SOI thickness resulted in an approximately 21.6% increase in gain. This improvement can be attributed to enhanced electrostatic gate control over the channel region as the SOI layer becomes thinner. The reduced SOI thickness minimizes the short-channel effects and enhances the coupling between the gate and the channel, resulting in improved transistor operation and higher gain. These findings highlight the importance of precisely controlling the SOI thickness during device fabrication to achieve optimal gain performance in TFET.

Fig. 6. Cross-sectional schematic of the TFET structure showing the SOI thickness, which refers to the thickness of the silicon layer above the BOX layer.

Fig. 7. Dependence of gain (A$_{\rm v}$) on SOI thickness. The gain increases as the SOI thickness decreases, reaching its maximum at 3 nm, due to improved electrostatic gate control and reduced short-channel effects.

VI. DRAIN UNDERLAP

To further improve the gain of the TFET source follower, the drain underlap technique is employed. Drain underlap refers to the deliberate introduction of a gap between the gate and the drain contact, as illustrated in Fig. 8. In this section, drain underlap length of 10 nm was applied to enhance gain performance by suppressing leakage current and improving electrostatic control. This structural modification is particularly effective in minimizing parasitic effects and short-channel effects (SCE), which can degrade analog performance in scaled devices. The primary reason for implementing drain underlap lies in its ability to suppress leakage current and mitigate SCE, which enhances the overall transistor operation. In practice, the method of introducing an underlap between the gate and drain has been employed to enhance the characteristics of TFET ^[20-22]. By reducing the electric field at the drain side, drain underlap minimizes the BTBT generation rate in the off state, as demonstrated in Fig. 9. This suppression of BTBT leakage current ensures better transistor performance and stability. Furthermore, Fig. 10 presents the energy band diagram under the drain underlap condition, confirming that the DITL effect is reduced, which strengthens the gate's ability to control the channel. Fig. 11 illustrates the gain (A${}_{\rm v}$) characteristics as a function of gate voltage, comparing the baseline TFET with the 10 nm underlap structure. The application of drain underlap resulted in an approximately 22% increase in gain. Moreover, by significantly reducing leakage current, the gain remains stable across the entire gate voltage range, which is critical for consistent analog signal processing in source follower operation. In summary, the implementation of a 10 nm drain underlap effectively suppresses leakage currents and mitigates SCEs, leading not only to improved gain but also to enhanced stability in TFET source follower performance.

Fig. 8. Cross-sectional view of the TFET structure showing the drain underlap region. The underlap, defined by the gap between the gate and the drain, is designed to suppress leakage current and mitigate short-channel effects.

Fig. 9. Comparison of band-to-band generation between the basic TFET and TFET with drain underlap.

Fig. 10. Comparison of energy band diagrams between a conventional TFET and a TFET with drain underlap. The introduction of the drain underlap modifies the energy band profile, reducing the DIBT effect.

Fig. 11. Gain (A$_{\rm v}$) comparison between the basic TFET and TFET with drain underlap as a function of gate voltage.

VII. DRAIN MATERIAL

To further enhance the gain of the TFET source follower, this study investigates the impact of replacing the material near the drain and the adjacent channel region from SiGe to Si. Fig. 12 illustrates the modified device structure, where the material substitution is applied specifically to optimize device performance. In this study, both the drain region and the 5 nm portion of the channel adjacent to the drain were changed from SiGe to Si. The primary reason for implementing this material change is to reduce the leakage current in the off state and to improve the gate control over the channel. Si has a wider bandgap compared to SiGe, which suppresses the BTBT generation rate in the off state. As shown in Fig. 13, the BTBT leakage current is significantly reduced when the region near the drain is composed of Si instead of SiGe. This reduction minimizes unwanted carrier generation in the off state, leading to improved device stability and reduced noise interference. Moreover, Fig. 14 presents the energy band diagram under the modified material condition. By replacing SiGe with Si, the DIBT effect is mitigated, as the wider bandgap of Si increases the energy barrier between the drain and the channel. This improved barrier control enhances the gate's ability to regulate the channel, resulting in a stronger coupling between the gate and the channel. The combination of reduced BTBT leakage and mitigated DIBT directly contributes to an increase in the gain of the TFET source follower. Fig. 15 confirms this result, showing a noticeable gain enhancement when the region near the drain and adjacent channel is switched to Si. In conclusion, substituting SiGe with Si in the drain and adjacent channel region effectively suppresses leakage current, mitigates short-channel effects, and enhances gate control, all of which collectively improve the gain of the TFET source follower.

Fig. 12. Cross-sectional view of the TFET structure with modified drain and channel regions. The drain region and the area adjacent to both the gate and drain are converted to Si instead of SiGe.

Fig. 13. Comparison of band-to-band generation between the basic TFET and TFET with a Si drain and adjacent channel material.

Fig. 14. Energy band diagram comparison between the basic TFET and TFET with a Si drain.

Fig. 15. Comparison of gain (A$_{\rm v}$) between the basic TFET and TFET with a Si drain. The graph shows that the TFET with a Si drain achieves higher gain, indicating improved performance due to the material substitution.

VIII. OPTIMIZED STRUCTURE ANALYSIS

To enhance the performance of the SF, multiple structural optimizations were applied simultaneously. These optimizations included applying SiGe material and optimizing the Ge ratio, optimizing the SOI thickness, implementing a drain underlap, and replacing the drain material with Si. Specifically, an SOI thickness of 3 nm was used, the drain underlap length was set to 10 nm, and the drain region and both the drain region and the 5 nm portion of the channel adjacent to the drain were changed from SiGe to Si. By integrating these modifications, the optimized TFET exhibited a significantly improved gain compared to both the conventional TFET and MOSFET. As shown in Fig. 16, the optimized TFET achieves a higher voltage gain across all gate lengths.

Quantitatively, the voltage gain of the optimized TFET at a 20 nm gate length is 0.936, compared to 0.757 for the basic TFET and 0.440 for the MOSFET. This represents an improvement of approximately 26.9% over the basic TFET and 53.1% over the MOSFET. This indicates that the structural modifications effectively mitigate short-channel effects while enhancing device performance. These results demonstrate that the proposed optimization strategies contribute to achieving a more efficient SF design, making the optimized TFET a promising candidate for advanced low-power analog applications.

Fig. 16. Gain (A$_{\rm v}$) comparison between MOSFET, TFET, and optimized TFET for gate lengths ranging from 200 nm to 20 nm.

IX. CONCLUSION

This study investigated the optimization of TFET structures to enhance the gain of the SF in CIS. With the increasing demand for high-resolution and efficient CIS, structural innovations were proposed to address the limitations of conventional MOSFETs and to overcome challenges posed by device scaling. The adoption of TFETs provided significant advantages, including reduced power consumption, lower noise, and enhanced performance. Key optimizations included tailoring the Ge composition in SiGe-based TFETs to achieve a balanced on-current and gain, with 50% Ge identified as the optimal ratio. Additionally, reducing the SOI thickness to 3 nm improved gate control, minimized short-channel effects, and enhanced device performance. The implementation of drain underlap further improved gain by suppressing BTBT leakage current and mitigating DIBT, thereby enhancing gate-channel coupling. Lastly, replacing the drain and adjacent channel material from SiGe to Si successfully reduced leakage current, improved energy barrier control, and resulted in a noticeable gain increase. These results indicate that these structural modifications can collectively enhance the gain of TFET SFs, demonstrating their potential to overcome the limitations of conventional scaling in CIS. These findings provide valuable insights for the development of high-resolution, low-noise CIS pixel structure with TFET SFs.