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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2025-08 (Vol.25 No.04)
  4. 10.5573/JSTS.2025.25.4.375
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References

1 
J. Lee, J. Jang, W. Lee, B. Suh, H. Yoo, and B. Park, ``4.2 A tri-band dual-concurrent Wi-Fi 802.11 be transceiver achieving-46dB TX/RX EVM floor at 7.1 GHz for a 4K-QAM 320MHz signal,'' Proc. of IEEE International Solid-State Circuits Conference (ISSCC), IEEE, vol. 67, 2024.DOI
2 
T.-M. Chen, M.-C. Liu, P.-A. Wu, W.-K. Hong, T.-W. Liang, and W.-P. Chao, ``A Wi-Fi tri-band switchable transceiver with 57.9 fs-RMS-jitter frequency synthesizer, achieving-42.6 dB EVM floor for EHT320 4096-QAM MCS13 signal,'' Proc. of IEEE Radio Frequency Integrated Circuits Symposium (RFIC), IEEE, 2023.DOI
3 
Y. Hu, W. Tao, and R. B. Staszewski, ``Nonlinearity-induced spur analysis in fractional-N synthesizers with $\Delta\Sigma$ quantization cancellation,'' IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 226-237, 2024.DOI
4 
Y. Hu, X. Chen, T. Siriburanon, J. Du, V. Govindaraj, and A. Zhu, ``A charge-sharing locking technique with a general phase noise theory of injection locking,'' IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 518-534, 2021.DOI
5 
W. S. Titus and J. G. Kenney, ``A 5.6 GHz to 11.5 GHzDCO for digital dual loop CDRs,'' IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp. 1123–1130, May 2012.DOI
6 
Y. Sun, J. Qiao, X. Yu, W. Rhee, B.-H. Park, and Z. Wang, ``A continuously tunable hybrid LC-VCO PLL with mixed-mode dual-path control and bi-level $\Delta$-$\Sigma$ modulated coarse tuning,'' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 9, pp. 2149-2158, Sep. 2011.DOI
7 
Z. Xu, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, and M.-C. F. Chang, ``A 70–78-GHz integrated CMOS frequency synthesizer for W-band satellite communications,'' IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 12, pp. 3206-3218, Dec. 2011.DOI
8 
M. V. Krishna, A. Jain, N. A. Quadir, P. D. Townsend, and P. Ossieur, ``"A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS,'' Proc. of ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), IEEE, 2014.DOI
9 
D.-G. Lee and P. P. Mercier, ``A sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of -256 dB,'' IEEE Journal of Solid-State Circuits, vol. 55, no. 6, pp. 1542-1552, June 2020.DOI
10 
Z. Yang, Y. Chen, J. Yuan, P.-I. Mak, and R. P. Martins, ``A 3.3-GHz integer N-type-II sub-sampling PLL using a BFSK-suppressed push–pull SS-PD and a fast-locking FLL achieving- 82.2-dBc REF spur and- 255-dB FOM,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 2, pp. 238-242, 2021.DOI
11 
Z. Zhang, X. Shen , Z. Zhang, and G. Li, ``4.7 A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL achieving 236.6fsrms jitter, -253.8dB jitter-power FoM, and -76.1dBc reference spur,'' Proc. of 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 86-88, 2023DOI
12 
X. Shen, Z. Zhang, Y. Che, Y. Li, Y. Zhang, and G. Li, ``A 0.144 mm$^2$ 12.5-16GHz PVT-tolerant dual-path offset-charge-pump-based fractional-N PLL achieving 72.9 fSRMs jitter, -271.5dB FoMN, and sub-10% jitter variation,'' Proc. of 2024 IEEE Custom Integrated Circuits Conference (CICC), IEEE, pp. 1-2, 2024.DOI
13 
M. Rossoni, S. M. Dartizio, F. Tesolin, G. Castoro, R. Dell'Orto, and A. L. Lacaita, ``A low-jitter fractional-N digital PLL adopting a reverse-concavity variable-slope DTC,'' IEEE Journal of Solid-State Circuits, vol. 60, no. 6, pp. 2122-2133, 2024.DOI
14 
[same as [12]]X. Shen, Z. Zhang, Y. Che, Y. Li, Y. Zhang, and G. Li, “A 0.144 mm2 12.5-16GHz PVT-tolerant dualpath offset-charge-pump-based fractional-N PLL achieving 72.9 fSRMs jitter, -271.5dB FoMN, and sub-10% jitter variation,” Proc. of 2024 IEEE Custom Integrated Circuits Conference (CICC), IEEE, pp. 1-2, 2024.DOI
15 
UW. Wu, C.-W. Yao, C. Guo, P.-Y. Chiang, L. Chen, and P.-K Lau, ``A 14-nm ultra-low jitter fractional-N PLL using a DTC range reduction technique and a reconfigurable dual-core VCO,'' IEEE Journal of Solid-State Circuits, vol. 56, no. 12, pp. 3756-3767, 2021.DOI
16 
T. Wu, P. K. Hanumolu, K. Mayarem, and U.-K. Moon, ``A 4.2 GHz PLL frequency synthesizer with an adaptively tuned coarse loop,'' Proc. of IEEE Custom Integrated Circuits Conference, IEEE, 2007.DOI