SheXu1
XieYisha1
LiuLintao1
GuoAiying1
-
(Shanghai University, Shangda Road 99, Shanghai 200444, China)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Phase-locked loop (PLL), charge pump (CP), voltage control oscillator (VCO), dual path
I. INTRODUCTION
With the growing need for increasing capacity and higher data rate, the wifi7 standard
was developed to promise faster and more robust wireless communication [1,2]. For the next-generation communications targeting 4096=QAW (Quadrature Amplitude
Modulation), the error-vector magnitude (EVM) contributed by the local oscillator
is expected to be as low as 0.5%, accounting for around 16% of the total EVM's budget
[3,4]. This stringent requirement presents significant challenges for designing frequency
synthesizers with high noise performance. The phase-locked loop (PLL) is a key component
in such frequency synthesizers, capable of generating the desired frequency from a
constant reference signal, typically derived from a crystal oscillator.
In addition to the stringent noise specifications, maintaining lock in the PLL under
varying temperature conditions is critical. If the PLL loses lock due to temperature
fluctuations, the local frequency may drift, leading to communication frequency shifts.
Therefore, once the PLL locks, it must remain in the locked state despite environmental
changes.
A common approach to extend the voltage-controlled oscillator (VCO) tuning range while
maintaining a low Kv is to incorporate a secondary tuning port to compensate for temperature
variations. This approach is shown in Fig. 1, which compares a dual-path PLL assisted by a linear amplifier (LA) (Fig. 1(a)) [6] and a secondary loop PLL with two CPs (Fig. 1(b)) [5]. While the dual path loop PLL (Fig. 1(b)) requires only a single charge pump (CP), making it easier to implement, we adopt
the dual-path PLL architecture for our design.
But there exists another challenge. Conventional VCOs typically exhibit a narrow tuning
range due to the low bias voltage of the NMOS varactors in this process technology.
To address this limitation, we propose the use of a negative Kv VCO (NKvVCO) instead
of a conventional positive Kv VCO.
In this brief, we present a 7.5-9.6 GHz PLL realized in a 22-nm Fully-Depleted Silicon-On-Insulator
(FD-SOI) CMOS process. The jitter performance of the PLL is ensured by four coupled
NKvVCOs and a half-charge pump (HCP). The additional path, named ATEMP, is employed
to extend the NKvVCO tuning range, enabling the PLL to maintain lock state even under
significant temperature variations.
This brief is organized as follows: Section II describes the overall PLL architecture
and implementation of the building blocks. The stability of the proposed PLL is discussed
in Section III. Measurement results are provided in Section IV, followed by the conclusion
in Section V.
Fig. 1. (a) Dual-path PLL and (b) secondary loop PLL.
II. PROPOSE PLL ARCHITECTURE
The overall architecture of the PLL is shown in Fig. 2. As previously described, the PLL consists of two tuning paths leading from the low-pass
filter (LPF) to the Negative Kv Voltage-Controlled Oscillator (NKvVCO). The indirect
path, referred to as ATEMP, is designed to extend the tuning range of the NKvVCO by
utilizing a larger Kv than the common path. To mitigate noise introduced by this additional
tuning path and to stabilize the loop, a large RC filter is implemented within the
automatic temperature compensation (ATEMP) path. To improve the noise performance
of the NKvVCO, it is implemented using two coupled counterparts. This design addresses
the inherent limitations of the FD-SOI process, which will be discussed in detail
in subsequent sections. A conventional swallow and pulse divider, modulated by a third-order
delta-sigma modulator (DSM), is employed. The modulator accepts continuous program
input bits, which range from 93 to 120. The phase-frequency detector (PFD) is realized
using standard CMOS logic gates and flip-flops (DFF), with the option for selectable
dead-zone time. To offer flexibility in loop parameters, the charge pump (CP) is programmable,
with current levels ranging from 10 $\mu$A to 2 mA. Additionally, the CP operates
in half-mode when the loop is locked, which helps to improve linearity and reduce
phase noise. The DSM and Auto-Frequency Calibration (AFC) are implemented in Verilog.
Fig. 2. Proposed dual loop architecture.
1. CP
The current-steering charge pump (CP) [7] is widely used in industry due to its robustness and excellent up down current mismatch
performance. The proposed half-charge pump (HCP) is shown in Fig. 3. It operates at 1.8 V supplied by a low-dropout regulator (LDO), with an output voltage
range of 700 mV to 1.1 V. The HCP functions as a conventional CP when the loop is
in the process of locking. A lock detector, LD monitors the state of the loop . Once
the loop is locked, the up-current cells are disabled, and the offset current cells
remain active to inject offset charge into the LPF.
Fig. 3. Proposed HCP architecture.
To reduce its noise, we employ a source negative feedback technique, which is commonly
used in low-noise circuit design. The thermal noise of a MOSFET can be expressed as
where $I^2_n$ is the noise current, $k$ is Boltzmann's constant, $T$ is the temperature,
$\gamma $ is a process-dependent constant, and $g_m$ is the transconductance of the
MOSFET. The transconductance $g_m$ is given by
where $I$ is the current, ${\mu }_n$ is the electron mobility, $c_{ox}$ is the oxide
capacitance, and $W/L$ is the width-to-length ratio of the MOSFET. In most cases,
the current is fixed by design specifications, so the only design element is the ratio
of width to length.
To further improve the noise performance, we connect a resistor in series with the
source of the MOSFET [14], as shown in Fig. 3. This technique reduces the effective transconductance $g_{m,effect}$ and is expressed
as
where $R$ is the series resistor. This method significantly improves the noise performance
by reducing the effective $g_m$, and thus lowering thermal noise.
The current of CP could be programed from 10 uA to 2 mA with 10 uA resolution. Each
current cell is with a 15 k$\Omega$ resistor. When the PLL is locked, the up-current
path of the CP is disabled. Instead, the offset current cells continuously inject
a constant offset current to introduce a phase offset, thereby improving the linearity
of the CP, as shown in Fig. 4. This also reduces the complexity of designing the up-current cells, as they no longer
contribute to noise once the loop is locked.
Fig. 4. The linearity of normal mode CP (a) and half mode CP (b).
Additionally, the switch is moved from the current path to the gate of the cascaded
transistor, eliminating the need to account for the resistance of the switches in
their open state. The switches used in the design are shown in Fig. 5 (for example, in Fig. 5(a), when en $=1$ and enb $=0$, nodes a and b are shorted; when en $=0$ and enb $=1$,
nodes a and b are disconnected, and node b is pulled to $Vdd$ ). The operational amplifiers
(opamps) used for current biasing in [7] have been removed, as the CP operates in half-mode when the loop is locked.
Fig. 5. Switch of up current and offset current (a) and down current (b).
2. Divider
The architecture of the divider is shown in Fig. 6. Fig. 6(a) illustrates a conventional pulse-swallowing divider. In this design, the prescaler
operates in a $\div(N+1)$ mode when the mod signal is 1, and in $\div N$ mode when
the mod signal is 0. The output of the Scounter changes from 1 to 0 after S prescaler
periods. To ensure that the modulation state (mod) of the prescaler does not change
during operation (for instance, ensuring mod stays at 1 while the prescaler operates
in mode 1), the output of the Scounter must be synchronized with the output of the
prescaler through a D flip-flop (DFF). Therefore, the input to the Scounter should
be greater than 1.
When the Scounter aims for 0, this indicates that mod should remain 0. Conversely,
when the Scounter aims for 1, mod=1 will only occupy one of the P periods (for example,
if P $=8$, the prescaler will operate in mod $=1$ for just one prescaler period, followed
by 7 prescaler periods in mod $=0$). This functionality is controlled by the reload
signal. To achieve this, the dashed-line portion is added to the conventional divider
like in Fig. 6(b). This design allows the divider to be set from 93 to 120 without constraint on the
input.
Based on [8], we developed a $\div 8/9$ dual-modulus prescaler. The circuit and its operating
principle are shown in Fig. 7 and Fig. 8. The pulse-swallowing logic is integrated within the TSPC flip-flops to enhance the
speed (see Fig. 7). As shown in Fig. 8, when the gates of M2 and M3 are both high, the circuit will swallow a clock pulse
when operating in $\div9$ mode. Considering the modulation from the Delta-Sigma Modulator
(DSM), the Scounter cannot be set to its maximum value (e.g., a 2-bit Scounter cannot
be set to 3, as the DSM may add a value greater than 3). To address this issue, the
input of the divider is directly controlled by the DSM, with any overflow being handled
appropriately.
Fig. 6. Conventional pulse swallowing divider (a) and the proposed divider (b).
Fig. 7. The architecture of the proposed $ \div 8/9$ prescaler.
Fig. 8. Working principle of the prescaler.
3. ATEMP
The ATEMP path is controlled by a selectable-gain operational amplifier (opamp) and
a large RC filter. The opamp configuration is shown in Fig. 9. In this design, Op1 and Op2 function as buffers, and all opamps are rail-to-rail
amplifiers to maximize output swing. The resistors R1 and R2 are equal, as are R3
and R4. The gain of the opamp circuit is given by
The loop stability is highly sensitive to the opamp gain, and this will be further
analyzed in Section III. The large RC filter is implemented to effectively attenuate
noise from the opamp, improving the overall noise performance of the loop.
Fig. 9. The selectable gain opamp.
4. NKvVCO
In the FD-SOI 22-nm process, the capacitance-voltage (C-V) curve of the varactor is
shown in Fig. 10(a) (assuming source and drain is positive node and gate is negative node). The steepest
point of this C-V curve differs from that of conventional varactors, such as those
in the TSMC 65-nm process (Fig. 10(b)). As shown in Fig. 10, the transition point in Fig. 10(a) appears at -0.2 V, whereas in Fig. 10(b), it appears at 0 V. A conventional VCO with positive Kv using A-MOS varactors in
the FD-SOI process demonstrates good linearity and tuning range at lower control voltages
(e.g., between 0.5 V and 0.9 V as shown in Fig. 10(c)). However, this conflicts with the output range of the charge pump (CP), which spans
from 0.7 V to 1.1 V.
A common approach to adjust the tuning voltage is to add additional capacitors and
resistors to bias varactors, as depicted in Fig. 11(e). However, the inclusion of resistors introduces noise and deteriorates phase noise
performance, which is unacceptable in our design. Our VCO operates at a 1.5 V supply
and swings from 0 to 1.4V. To address the issue mentioned above, instead of applying
the tuning voltage to the positive node (Fig. 11(c)), we apply it directly to the negative node (Fig. 11(d)), resulting in a NKvVCO, as shown in Fig. 11(a). This design optimizes the VCO's tuning range and noise performance without requiring
additional circuitry or sacrificing phase noise. To further improve phase noise performance,
our VCO architecture consists of two identical VCOs, as shown in Fig. 11(b), providing a 3 dB improvement in phase noise as in [15].
The tuning curves for both positive and negative Kv are shown in Figs. 10(c) and 10(d), with their corresponding Kv values depicted in Figs. 10(e) and 10(f). It could be seen that the positive Kv shows good linearity between 0.5 V and 0.9
V which is not suitable for our design. Whereas the negative Kv shows good linearity
between 0.7V and 1.1 V which is perfect for out design.
Fig. 10. he C-V curve of the var in (a) FD-SOI 22-nm and (b) tsmc65. VCO toning
curve of applying Vtone directly (c) on positive and (d) negative node. (e) and (f)
are Kv of (c) and (d).
Fig. 11. VCO architecture(a), two coupled VCO(b), Vtone on positive node(c), Vtone
on negative node(d) and varactor bias circuit(e).
III. STABILITY ANALYSIS
The small-signal model of the system is shown in Fig. 12.
Fig. 12. Linear model of the dual loop PLL.
The LF is simplified as a second order low pass filter for simplicity without sacrificing
accuracy. The open-loop gain $Ho(s)$ can be expressed as
For simplification, we model the low-pass filter (LPF) as a second-order low-pass
filter. Let the following substitutions be made
Substitute (6), (7), (8) into (5). The open loop gain could be rewritten as (9)
We note there is a zero in the denominator which is located at
${\omega }_{p4}$ are very low for big resistor and capacitor, so the closed loop's
phase would drop below zero. If ${\omega }_{z2}<{\omega }_{z1}$, the ${\omega }_{z\mathrm{2}}$
would compensate ${\omega }_{p{4}}$ to eliminate its deterioration in phase noise.
Since ${\omega }_{p4}$ is typically very low for large resistors and capacitors, the
closed-loop phase response will eventually drop below zero. If ${\omega }_{z2}<{\omega
}_{z1}$, the zero at ${\omega }_{z\mathrm{2}}$ will compensate for the pole at ${\omega
}_{p\mathrm{4}}$, effectively mitigating its adverse effects on phase noise. For a
more comprehensive derivation, please refer to [16].
Simulations of the phase and gain for a conventional third-order type-2 loop and the
proposed loop have been performed. As expected, the gain decreases by 40 dBc/Hz at
low frequencies and by 60 dBc/Hz after ${\omega }_{p{4}}$. Beyond ${\omega }_{z{2}}$,
the loop behaves similarly to a conventional third-order type-2 loop.
The gain of the operational amplifier in the ATEMP path must be carefully selected
to ensure proper performance. The Bode diagrams of the phase and gain for both loops
are shown in Fig. 13.
Fig. 13. The bode diagram of single loop (a) (b) and dual loop (c) (d).
IV. MEASUREMENT RESULTS
The synthesizer is integrated into a 22-nm FD-SOI RF CMOS process, with the core chip
area measuring 0.9 mm$^2$, excluding the digital components. PN spectrum according
to the linear model is show in Fig. 14. Fig. 15 shows the fabricated chip. During the measurement process, the gain of the second
tuning path is selected and kept constant.
Fig. 14. PN spectrum according to the linear model.
Fig. 15. Chip micrograph.
Figs. 16 and 17 presents the measured phase noise and timing jitter of the PLL with 59.05 and 55.7
divide ration. The spur level is shown in Fig. 18. The phase noise is recorded at $-119.02$ dBc/Hz at a 1 MHz offset, and the root-mean-square
(rms) jitter is 56.4 fs. Table 1 summarizes the performance of the PLL and compares it with recent works in low-jitter
PLL design. Despite being based on a traditional charge pump (CP) architecture, the
phase noise and jitter performance of our PLL remain highly competitive, even when
compared to sub-sampling and injection-locked architectures.
Fig. 16. Measured phase noise with 59.05 divide ratio.
Fig. 17. Measured phase noise with 55.7 divide ratio.
Fig. 18. Measured spur level.
Table 1. Performance summary and comparison.
|
|
This work
|
Lee
JSSC'20[9]
|
Yang
VLSI'22[10]
|
Zhang
ISSCC'23[11]
|
Shen
CICC'24[12]
|
Rossoni
JSSC'24[13]
|
|
Architecture
|
CP-PLL
|
SS-PLL
|
SS-PLL
|
SSPLL
|
CP-PLL
|
BBPLL
|
|
CMOS process
|
22nm
|
65nm
|
65nm
|
40nm
|
40nm
|
28nm
|
|
Fout
/FTR(GHz)
|
8.5
/7.5-9.6
|
2.4
/NA
|
3.296
/NA
|
2.5
/2.25-2.75
|
14
/12.5-16.0
|
NA
/8.75-10.25
|
|
Fref(MHz)
|
160
|
100
|
103
|
62.5
|
156.25
|
250
|
|
Rms jitter (fs)
/(integrated range)
|
56.379
/(10kHz to 100MHz)
|
161
/(10kHz to 100MHz)
|
65.9
/(1kHz to 40MHz)
|
236.6
/(1kHz to 100MHz)
|
72.85
/(1kHz to 100MHz)
|
57.3
/(1kHz to 100MHz)
|
|
spur(dBc)
|
-65
|
-67
|
-82.2
|
-76.1
|
-84.2
|
-63.4
|
|
Power (mW)
|
86.9
|
0.93
|
7.53
|
0.74
|
12
|
17.5
|
|
Core Area ({mm}$^2$)
|
0.9
|
0.42
|
0.21
|
0.197
|
0.144
|
0.21
|
|
(dB)
|
-245.6
|
-256
|
-255
|
-251
|
-252
|
-253.5
|
${FOM}^*=10\cdot \log \left[{\left(\frac{{\sigma }_{rms}}{1s}\right)}^2\cdot \left(\frac{\text{Power}}{\text{1
mW}}\right)\right]$
V. CONCLUSION
A low jitter, low phase noise with dual path PLL is demonstrated. The dual path architecture
promises the lock state. Half CP in lock state and the negative KvVCO improve the
noise performance. The improved impulse-swallow divider shows flexible input. Each
block is powered by LDO integrated in the PLL. The prototype 7.5-9.6 GHz PLL realized
in 22-nm FD-SOI RF CMOS process achieves 56.379 fs rms-jitter and $-65$ dBc spur.
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Xu She was born in Chongqing, China, in 2000. He received his B.Sc. degree in microelectronics
science and engineering in 2019 from School of Microelectronics, Shanghai University
(SHU), Shanghai, China. He is currently pursuing a post-graduate degree in integrated
circuit science and engineering at SHU. His research interests include analog/mixed-signal
IC design, focusing on low-low jitter frequency synthesizers for mmW application.
Yisha Xie was born in Fujian, China in 2001. In 2019, she obtained her bachelor of
engineering degree from the School of Integrated Circuits at Tianjin University of
Technology in Tianjin, China. She is currently pursuing a master's degree in microelectronics
at Shanghai University. Her research focus is on the design of SerDes equalizers.
Lintao Liu was born in Chongqing, China, in 2002. He received his B.Sc. degree in
microelectronics science and engineering in 2020 from the School of Microelectronics,
Shanghai University (SHU), Shanghai, China. He is currently pursuing a post-graduate
degree in integrated circuit science and engineering at SHU. His research interests
focus on power management.
Aiying Guo received her bachelor's degree in communication engineering from Taiyuan
University of Technology in 2007, a master's degree in microelectronics and solid-state
electronics from Beijing University of Technology in 2009, and a Ph.D. degree in control
science and engineering from Shanghai University in 2017. She is an associate professor
at the School of Microelectronics, Shanghai University. Her research interests include
mixed-signal IC design, silicon-based micro-display, and weak signal processing. She
has also led and participated in research projects funded by the National Natural
Science Foundation of China and industry.