X. Gao, O. Burg, H.Wang,W.Wu, C.-T. Tu, and K. Manetakis,
“9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dBFOM,
digital fractional-N sampling PLL in 28nm CMOS,”
Proc. of 2016 IEEE International Solid-State Circuits Conference
(ISSCC), San Francisco, CA, USA, 2016.
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