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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2025-06 (Vol.25 No.03)
  4. 10.5573/JSTS.2025.25.3.292
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References ▼

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J. Kim, H. Yoon, Y. Lim, Y. Lee, Y. Cho, and T. Seong, “16.2 A 76fsrms jitter and -40dBc integrated-phase-noise 28-to-31GHz frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators and background loop-gain optimization,” Proc. of 2019 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2019. [CrossRef]

[2]

Z. Yang, Y. Chen, S. Yang, P.-I. Mak, and R. P. Martins, “16.8 A 25.4-to-29.5GHz 10.2mW isolated sub-sampling PLL achieving -252.9dB jitter-power FoM and -63dBc reference spur,” Proc. of 2019 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2019. [CrossRef]

[3]

Y. Hu, X. Chen, T. Siriburanon, J. Du, Z. Gao, and V. Govindaraj, “17.6 A 21.7-to-26.5GHz charge-sharing locking quadrature PLL with implicit digital frequencytracking loop achieving 75fs jitter and -250dB FoM,” Proc. of 2020 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2020. [CrossRef]

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E. Thaller, R. Levinger, E. Shumaker, A. Farber, S. Bershansky, and N. Geron, “32.6 A K-band 12.1-to-16.6GHz subsampling ADPLL with 47.3fsrms jitter based on a stochastic flash TDC and coupled dual-core DCO in 16nm FinFET CMOS,” Proc. of 2021 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021. [CrossRef]

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W. Wu, C.-W. Yao, K. Godbole, R. Ni, P.-Y. Chiang, and Y. Han, “A 28-nm 75-fsrms analog fractional-N sampling PLL with a highly linear DTC incorporating background DTC gain calibration and reference clock duty cycle correction,” IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1254-1265, May 2019. [CrossRef]

[6]

M. Mercandelli, A. Santiccioli, A. Parisi, L. Bertulessi, D. Cherniak, and A. L. Lacaita, “A 12.5-GHz fractional- N type-I sampling PLL achieving 58-fs integrated jitter,” IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 505-517, February 2022. [CrossRef]

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J. Lee, J. Jang, W. Lee, B. Suh, H. Yoo, and B. Park, “4.2 A tri-band dual-concurrent Wi-Fi 802.11be transceiver achieving 􀀀46dB TX/RX EVM floor at 7.1GHz for a 4KQAM 320MHz signal,” Proc. of 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024. [CrossRef]

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H. Liu, D. Tang, Z. Sun, W. Deng, H. C. Ngo, and K. Okada, “A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS,” Proc. of 2018 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2018. [CrossRef]

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X. Gao, O. Burg, H.Wang,W.Wu, C.-T. Tu, and K. Manetakis, “9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dBFOM, digital fractional-N sampling PLL in 28nm CMOS,” Proc. of 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016. [CrossRef]

[10]

S. Kim, “Design of fractional-N digital PLL for IoT application,” Journal of IKEEE, vol. 23, no. 3, pp. 800-804, 2019. [CrossRef]

[11]

W. Wu, C.-W. Yao, C. Guo, P.-Y. Chiang, L. Chen, and P.- K. Lau, “A 14-nm ultra-low jitter fractional-N PLL using a DTC range reduction technique and a reconfigurable dualcore VCO,” IEEE Journal of Solid-State Circuits, vol. 56, no. 12, pp. 3756-3767, December 2021. [CrossRef]

[12]

D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of IEEE, vol. 54, no. 2, pp. 329- 330, February 1966. [CrossRef]

[13]

M. Mercandelli, A. Santiccioli, A. Parisi, L. Bertulessi, D. Cherniak, and A. K. Lacaita, “A 12.5-GHz fractional- N type-I sampling PLL achieving 58-fs integrated jitter,” IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 505-517, February 2022. [CrossRef]

[14]

S. M. Dartizio, F. Tesolin, G. Castoro, F. Buccoleri, L. Lanzoni, and M. Rossoni, “4.3 A 76.7fs-integrated-jitter and -71.9dBc in-band fractional-spur bang-bang digital PLL based on an inverse-constant-slope DTC and FCW subtractive dithering,” Proc. of 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023. [CrossRef]

[15]

H. Zhang, Y. Zhu, M. Osada, and T. Iizuka, “A 96fsrmsjitter, -70.6dBc-fractional-spur cascaded PLL employing two MMDs with shared DSM for quantization noise cancellation,” Proc. of 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025.