The increasing demand for higher data rates, low latency, and reliable communication continues to drive the development of advanced wireless protocols and systems. Emerging applications such as next-generation radar systems, high-frequency satellite communications, and 5G mmWave infrastructure operate in high-frequency bands and require highly robust, low-jitter local oscillators (LOs)　to maintain signal integrity and meet stringent performance criteria. To fulfill these requirements, phase-locked loops (PLLs) are critical components used to generate high-frequency signals with minimal jitter. This research aims to design a high-frequency 13-GHz fractional-N sampling PLL to achieve ultra-low jitter performance suitable for next-generation wireless and high-frequency radar applications.
PLL structures that detect phase errors by using sampling techniques are being actively studied because they are easy to achieve relatively low integrated jitter compared to other structures. However, challenges persist in reducing quantization noise (QN) and managing spurious tones. The conventional sub-sampling PLL architecture has been widely employed for ultra-low jitter applications due to its ability to directly sample the reference signal, effectively minimizing phase noise contributions from subsequent stages [1]-[4]. However, sub-sampling PLLs do not use a multi-modulus divider (MMDIV) for locking, making them vulnerable to harmonic locking, which increases the risk of instability and unreliable operation under varying conditions. Due to these drawbacks, research on digital-to-time converter (DTC)-based analog sampling PLL architecture has been actively pursued recently [5]-[7]. Sampling PLLs use MMDIV to achieve stable lock, providing robust performance even in fractional-N applications. Although this results in slightly higher power consumption and increased jitter compared to ideal conditions, it significantly enhances overall stability, making it more suitable for demanding environments. For this reason, the PLL in this work is implemented as a sampling PLL structure.
One of the problems of PLL structures that adopt sampling-based phase detector (PD) occurs during loop switching to fine loop after coarse locking. When loop switching to a fine loop occurs after coarse locking by charge-pump PLL (CPPLL), additional fine lock time is consumed and fine locking by the fine loop is performed due to the large difference in loop gain between the two loops and the difference in locking phase offset. This time-consuming fine locking process carries the potential risk of even performing unstable locking depending on chip environmental changes, bandwidth, sampling phase detector gain ($K_{SPD}$), etc. To mitigate this problem, this work proposes a phase offset calibration technique applicable to DTC based analog sampling PLL architecture. By directly compensating for locking phase offset differences between coarse and fine loops, this method enables faster fine lock time and smoother transitions between different phase locking conditions. In addition to this technique, the PLL also incorporates DTC gain calibration and reference voltage calibration techniques, which effectively compensate non-linearity and maintain ultra-low jitter over process, voltage, and temperature (PVT) variations. Furthermore, a reconfigurable dual-core LC voltage-controlled oscillator (VCO) provides flexibility in balancing power consumption and performance, allowing the PLL to adapt to various operating conditions and optimize both power efficiency and jitter performance. The PLL achieves rms jitter as 138.5 $fs_{rms}$ while consuming only 4.12 mW. The PLL core is implemented in a 28 nm CMOS process and occupies 0.47 mm². With a figure-of-merit (FoM) of –251 dB, this work is considered a promising new alternative compared to existing state-of-the-art designs.

 Figure 1 shows the block diagrams of the proposed high-performance DTC-based analog sampling PLL, schematic of the sampling phase detector (SPD) and voltage-to-current stage ($G_M$), and schematic of the DTC. MMDIV, driven by a delta-sigma modulator (DSM), enables fractional-N synthesis. The expected phase error, $Φ_e$, appears as a quantization error (QE) from the DSM. By scaling this QE with the estimated DTC gain, the DTC effectively removes QE from the feedback clock. This QE removal technique significantly reduces the required linear operating range of the SPD after PLL locking from several VCO cycles down to a few picoseconds.
The SPD comprises a ramp generator and a sample-and-hold circuit. When the rising edge of CLKDTC triggers a voltage ramp with an extremely high dV/dt slope, the rising edge of CLKFB samples it, converting the phase error into a sampled voltage, $V_{CTRL}$_$_P$. After passing through a first-order RC filter to remove high-frequency noise and suppress reference spurs, the sampled output voltage drives two paths: one directly tunes the VCO ($K_{VCO}$_$_P$), providing proportional gain $K_{VCO}$_$_P$; the other passes through a $G_M$ stage and an integration capacitor CI to generate $V_{CTRL}$_$_I$ for the VCO ($K_{VCO}$_$_I$).
The SPD gain, $K_{SPD}$, is given by:

$K_{\rm SPD} = \frac{\Delta v}{\Delta \Phi} = \frac{K_{\rm SLOPE}}{2\pi \cdot f_{\rm REF}}$

 $K_{SLOPE}$ refers to the slope of $V_{SLOPE}$ generated by slope gen circuit. In this work, by using $f_{REF}$ = 100 MHz and $K_{SLOPE}$ = 15 GV/s, $K_{SPD}$ ≈ 150/(2π), a remarkably high $K_{SPD}$ gain was achieved. And the open-loop gain A(s) of the sampling PLL is given as follows:

$A(s) =K_{\rm SPD}(s)\cdot \left(\frac{K_{\rm VCO\_P}}{s} +\frac{gm}{{\rm s}C_{\rm I}}\cdot \frac{K_{\rm VCO\_I}}{s}\right)$

 As a result, the loop gain is already sufficiently high due to the high $K_{SPD}$, the $G_M$ current (gm) can be designed to be quite small (in this work, < 300 nA). A smaller $G_M$ current also tends to reduce the size of CI required for loop stability. By employing a proportional-integral (PI) filter configuration without traditional resistive elements, the loop filter (LF) introduces less noise. Furthermore, using a smaller $K_{VCO}$_$_I$/$K_{VCO}$_$_P$ ratio allows for a reduced $C_I$, enabling a more area-efficient LF implementation.
By adopting a subsampling phase detector (SSPD), the noise generated by the MMDIV can be eliminated. However, in this paper, we retain MMDIV to ensure design flexibility for the SPD, accepting a slight degradation in noise performance. The SPD is implemented as a ramp generator to enable precise control of $K_{SPD}$. By using an MMDIV, the operating frequency of the ramp generator can be lowered to $f_{REF}$, allowing implementation with a simple RC charging circuit and thus providing a wide operating range. When $K_{SPD}$ is small, the SPD exhibits a wide linear operating range, making it suitable for the initial locking phase. Conversely, when $K_{SPD}$ is high, it can more effectively suppress $G_M$ noise in steady-state operation after fine locking. As shown in Figure 1, once the CPPLL-based coarse loop achieves coarse locking, the system smoothly transitions to the fine loop through a phase offset calibration system. This technique effectively mitigates the unstable fine locking issues caused by the phase difference in the locking phase offset between the coarse loop and the fine loop when moving from PFD and CP based coarse locking to SPD and $G_M$ based fine locking, thereby reducing the associated penalty on fine lock time. The DTC gain calibration technique is essential for achieving low in-band phase noise performance and low spurious tones. The comparator-based DTC gain calibration described in [8], [9] enables easy calibration of analog PLLs without requiring a time-to-digital converter (TDC). This calibration is performed in the background to maintain performance under PVT variations.

1. Phase Offset Calibration for Analog Sampling PLL

  The sampling PLL loop that performs fine locking achieves effective noise suppression by employing a high-gain SPD and uses a frequency divider to ensure stable fine locking. Furthermore, because the quantization error caused by the DSM used for fractional-N synthesis is eliminated by the DTC, there is an advantage of being able to use an SPD with a small linear operating range to achieve high gain. However, in this case, the phase locking points of the coarse loop and the fine loop are different, so a phase offset occurs. This problem is especially aggravated when the fine loop has very high gain, with a $K_{SPD}$ of 10 GV/s or more. To achieve fast locking time and stable loop switching, the switching time and switching conditions between the two loops must be considered. If loop switching occurs outside the locking range of the fine loop, the additional phase-locking process may increase the locking time and lead to unstable operation. Figure 2 illustrates a timing diagram showing the different locking phase offsets of the two loops.

  To compensate for this issue, [10] proposed a digital phase offset calibration technique applied to a digital sub-sampling PLL. In this work, a novel phase offset calibration circuit applicable to analog sampling PLL to improve the stability and efficiency of loop switching is proposed. Figure 3 shows a block diagram of the proposed approach. While coarse phase locking is performed, the sampling voltage ($V_{CTRL}$_$_P$) from the fine loop SPD is monitored via a 3-level comparator. By using information about which direction the phase error occurs, an appropriate offset current is added to the charge pump (CP_OFFSET) in the coarse loop, thereby applying a phase offset. As a result, coarse locking is performed so that the phase offset of fine locking almost matches.

  One important consideration is the potential race condition between the offset compensation loop and the coarse loop. Therefore, it is necessary to set the Δ$V_{step}$ of the offset compensation loop to an appropriate value to match the bandwidth properly. How to set V_TH_H and V_TH_L, which are the operating reference voltages of the 3-level comparator, is also a very important issue that must be considered for the accurate operation of phase offset calibration. If the Δ$V_{TH}$ (Δ$V_{TH}$ = V_TH_H – V_TH_L) range is set too wide, the seamless switching effect by phase offset calibration will be reduced, and if it is set too narrow, the calibration time becomes excessively long, making the coarse lock stage overly slow. It is important to note that the goal of this calibration is not to achieve fine lock, but to create a phase offset with enough accuracy to enable seamless switching. Through system simulation, it was confirmed that successful seamless switching was performed while maintaining the coarse lock time appropriately when the voltage range of Δ$V_{TH}$ was set to about 2 to 3% of the VDD level of the SPD. For example, if VDD = 1.0 V, setting Δ$V_{TH}$ to around 0.02 – 0.03 V is suitable. With this approach, a higher $K_{SPD}$ reduces the allowable phase error, thus enabling more precise calibration. If VDD = 1.0 V and $K_{SPD}$ = 1 GV/s, a 2% threshold range corresponds to a phase error tolerance of about ±10 ps. Increasing $K_{SPD}$ to 10 GV/s reduces the allowable phase error to only ±1 ps. In other words, with higher SPD gain, more refined calibration can be performed, ensuring seamless loop switching irrespective of the gain of SPD. Although narrowing the Δ$V_{TH}$ range further could yield even higher calibration accuracy but since a sufficiently successful seamless switching is already performed, a smaller Δ$V_{TH}$ range only prolongs the coarse lock time without providing additional practical benefits.
In this study, to apply the phase offset calibration technique through analog CPPLL, the phase offset according to the OFFSET_CTRL digital control code output through the digital calibration circuit is intentionally given to the PLL through CP_OFFSET. In the case of sampling PLL in this work, the phase locking is performed so that the feedback clock slightly lags the reference clock, as shown in Fig. 2. To match this in the coarse loop, an additional offset current is added to the down current IDN of the CP, so that the total down current ($I_{DN}$_$_{SUM}$ = $I_{DN}$ + $I_{OFFSET}$) is set to be larger than the up current IUP. This allows the CPPLL to perform coarse locking with an accurate phase difference matching the locking point of the fine loop. Figure 4 is a schematic of the implemented CP_OFFSET circuit. When the CPPLL is locked by CP_OFFSET in a steady state, the UP and DN pulse widths within one reference clock period adjust so that the net charge flow is zero, fixing a certain phase difference $Ф_{OFFSET}$ between the reference and feedback signals. A simple charge-balance analysis yields an exact expression for the phase offset $Ф_{OFFSET}$ as a function of $I_{OFFSET}$:

$\Phi_{\rm OFFSET} = 180^\circ \cdot \frac{I_{\rm OFFSET}}{2\cdot I_{\rm CP} + I_{\rm OFFSET}}$

  $I_{CP}$ is the nominal UP/DN current ($I_UP, I_DN$), and $I_{OFFSET}$ is the offset added to the DN side. If $I_{OFFSET}$ is sufficiently smaller than $I_{CP}$ ($I_{OFFSET}$ << $I_{CP}$), the equation can be approximated by:

$\Phi_{\rm OFFSET} \cong 90^\circ \cdot \frac{I_{\rm OFFSET}}{I_{\rm CP}}, ~(I_{\rm OFFSET} \ll I_{\rm CP})$

  For instance, if $I_{OFFSET}$ is 10% of $I_{CP}$, then the resulting offset is about 9°. Conversely, to find the corresponding $I_{OFFSET}$ after determining the target phase offset, the above formula can be expressed as follows:

$I_{\rm OFFSET}= 2\cdot I_{\rm CP} \cdot \frac{\Phi_{\rm OFFSET}}{180^\circ - \Phi_{\rm OFFSET}}$

  and the approximation of that inversion becomes:

$I_{\rm OFFSET} \cong I_{\rm CP} \cdot \frac{\Phi_{\rm OFFSET}}{90^\circ}, ~(I_{\rm OFFSET} \ll I_{\rm CP})$

  This provides a simple guideline for determining how large an offset current is needed for a desired phase offset $Ф_{OFFSET}$.

  While the equation suggests that an offset approaching 180° is mathematically possible by increasing $I_{OFFSET}$, as a rule of thumb, an offset above ~90° is difficult to maintain this stable state in a CPPLL. There are two issues that arise, the first is the ±180° phase detection limit. A PFD fundamentally relies on distinguishing which signal (CLKDTC or CLKFB) arrives first within ±180°. As $Ф_{OFFSET}$ approaches 180°, even small noise or disturbances can flip the perceived polarity of PFD, causing a sudden unlock or phase inversion. The second issue is the highly asymmetric loop gain. If $I_{OFFSET}$ becomes comparable to, or greater than, $I_{CP}$, the loop becomes heavily skewed, requiring one pulse ($I_{UP} or I_{DN}$) to be almost the entire reference period. Small variations then cause large swings in output phase, threatening stable lock. Because of these constraints, ~90° is viewed as the practical upper bound for a reliably stable phase offset. Typically, $I_{OFFSET}/I_{CP}$ stays well below 0.5 to reduce the risk of loop instability, which typically keeps the $Ф_{OFFSET}$ < 45°.

2. DTC Gain Calibration

  For fractional-N frequency synthesis in a sampling PLL, the division ratio of the MMDIV is modulated by a DSM to achieve an average fractional division ratio. In this process, QN inevitably arises due to the QE of the DSM. To remove this additional noise introduced by the DSM, a DTC is employed. DTC creates a time delay based on the input digital control code, thus eliminating the QN generated by the DSM. The amount of time error that needs to be removed can be calculated as the product of the $T_{VCO}$ and the QE. To accurately remove this time error with the DTC, a DTC gain calibration circuit is used to match the LSB time delay of the DTC (Δ$T_{DTC}$) with the required amount of time error by finding the correct value of gain of DTC (DTC gain). This relationship is expressed by equations:

$T_{\rm VCO} \cdot {\rm QE} = \Delta T_{\rm DTC} \cdot {\rm DTC}_{\rm gain} \cdot {\rm QE}$

$\Rightarrow {\rm DTC}_{\rm gain} = \frac{T_{\rm VCO}}{\Delta T_{\rm DTC}}$

  Figure 5 shows the block diagram of the DTC gain calibration circuit. The calibration is based on the Least-mean square (LMS) algorithm. It operates by tracking the exact DTC gain value that suits the actual circuit conditions by utilizing the correlation between the phase error obtained through SPD and the quantization error QE. To minimize the effects of voltage or temperature variations that may occur during chip operation, the calibration continues in the background throughout the overall PLL operation. In addition, the bandwidth of calibration loop can be adaptively changed, allowing for quick convergence of the gain value during the initial gain-lock process while maintaining precise gain thereafter.
Additionally, there is a potential risk of incorrect outputs at the phase detection stage of the SPD due to the offset voltage of the comparator itself and the $G_M$ circuit in the fine loop. To mitigate this problem, a circuit that dynamically adjusts the reference voltage is added, compensating for the offset voltages of both the GM and the comparator so that the dynamic reference voltage is accurately determined. This circuit consists of a 1-bit DSM and a DAC, where the DAC output ΔV is set to about ~1 mV, enabling stable convergence.

3. Dual-core VCO

  Using a high-performance VCO with low phase noise (PN) characteristics is always an important part of PLL design. From this perspective, a design that gains PN performance while sacrificing power consumption by using a VCO with two inductor cores is a worthwhile option [11]. Leeson’s PN equation [12] can be expressed as follows:

${\rm PN} \propto \frac{f_{\rm OSC}^3 \cdot L}{V_{\rm OSC}^2 \cdot Q}$

  By reducing inductance (L) via parallel inductors while maintaining quality factor (Q), the dual-core VCO can enhance the phase noise performance by 3 dB, as shown in the equation. Figure 6 presents the schematic of the dual-core VCO implemented in this work. Because the improved phase noise performance approximately doubles the power consumption, the VCO is designed to operate in two different modes. This allows the user to choose either higher performance or lower power consumption depending on the application requirements.

 The fractional-N sampling PLL implemented in this work was layout-designed using a 28-nm CMOS process. Figure 7 is the layout view of the implemented PLL. The core area of the PLL is 0.47 mm2. The PLL has a frequency synthesis range of 13 to13.3-GHz, and the input reference clock is 108-MHz. The PLL consumes a total of 4.12 mW when the VCO is in dual-core mode.
Figure 8 is the post-layout transient simulation result of the PLL. (a) shows the locking process of a typical DTC-based sampling PLL without phase offset calibration. When the loop switching to the fine loop is performed after the coarse locking by CPPLL is completed, it can be confirmed that the additional fine locking process takes time. In addition, since the DTC gain value begins to converge to the correct value after the loop switching, additional locking time is consumed as well. (b) shows the process of performing coarse locking corrected by the proposed phase offset calibration and performing fine locking. Unlike (a), the coarse locking phase offset is adjusted by the phase offset calibration during the coarse locking process. As a result, it can be confirmed that the value of $V_{CTRL}$_$_P$, which indicates the progress of fine locking, converges before the loop switching occurs, and coarse locking is performed according to the fine locking phase offset. As a result, there is almost no need for an additional fine locking process after the loop switching, so there is almost no waste of time for fine locking. In addition to the advantage of fine locking time, it also has the advantage of being able to prevent unstable locking caused by high loop gain or bandwidth. The DTC gain also almost converges to the correct value during the coarse locking process, allowing the DTC to perform QE removal almost immediately without additional time consumption when entering fine locking.
Figure 9 compares the post-layout transient simulation results of the PLL locking and calibration processes across various CMOS process corners (ss, tt, ff). It confirms that the implemented PLL successfully achieves both lock and calibration under all simulated conditions.
Figure 10 shows the post-layout simulated phase noise spectrum of the PLL. At the PLL output frequency of 13.25-GHz, the rms jitter of the PLL is 138.5-fsrms with the dual-core VCO, integrated from 10 kHz to 100 MHz. Table 1 shows the performance comparison between the PLL implemented in this work and other analog fractional-N PLL works. The PLL implemented in this work achieves high frequency synthesis in the 13 GHz band and high-performance FoM of -251 dB with low power consumption.

  This work presents a 13-GHz fractional-N PLL using DTC-based sampling PLL structure for high-performance PLL design. It has good phase noise characteristics by suppressing $G_M$ noise using high-gain PD and removing quantization error using DTC. Additionally, stable loop switching is possible by the proposed phase offset calibration applicable to analog sampling PLL. The digital calibration circuits of PLL were designed at RTL level and PNR, and the analog core was implemented with 28 nm CMOS process. The operation and performance were verified through post-layout simulation.

  This work was supported by the BK-21 FOUR program through the National Research Foundation of Korea (NRF) under the Ministry of Education. The EDA tool was supported by the IC Design Education Center (IDEC), Korea.