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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  3. 2025-06 (Vol.25 No.03)
  4. 10.5573/JSTS.2025.25.3.284
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References ▼

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E. -S. Lee, S. -H. Lee, C. -H. Pyo, H. -S. Kim and J. -D. Han, “A 2-GS/s 6-bit Single-channel Speculative Loop-unrolled SAR ADC with Low-overhead Comparator Offset Calibration in 28-nm CMOS” J. Semiconductor Technology and Science, Vol. 24, No. 4, pp. 355-364, May. 2024. [CrossRef]

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H. -Y. Jung, W. -K. Do, C.-W. Park, J. -H. Ko, Y. -C. Jang, “A 12-bit 10-MS/s Pipelined SAR ADC Sharing Flash ADC and Residue Amplifier of Multiplying DAC” J. Semiconductor Technology and Science, Vol. 24, No. 2, pp. 128-137, Jan. 2024. [CrossRef]

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K. -H. Kim, J. -H. Baek, J. -H. Kim, H. -I. Chae, “Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique” J. Semiconductor Technology and Science, Vol. 21, No. 5, pp. 297-303, Oct. 2021. [CrossRef]

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Y. Krupnik, Y. Perelman, I. Levin, Y. Sanhedrai, R. Eitan, and A. Khairi, “112-Gb/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels,” IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1077- 1085, April 2020. [CrossRef]

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A. Khairi, Y. Krupnik, A. Laufer, Y. Segal, M. Cusmai, and I. Levin, “A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-based SerDes receiver with hybrid AFE capable of supporting long reach channels,” IEEE Journal of Solid-State Circuits, vol. 58, no. 1, pp. 8-18, January 2023. [CrossRef]

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J. Im, K. Zheng, C.-H. A. Chou, L. Zhou, J.W. Kim, and S. Chen, “A 112-Gb/s PAM-4 long-reach wireline transceiver using a 36-way time-interleaved SAR ADC and inverterbased RX analog front-end in 7-nm FinFET,” IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 7-18, January 2021. [CrossRef]

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B.-J. Yoo, D.-H. Lim, H. Pang, J.-H. Lee, S.-Y. Baek, and N. Kim, “6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 wireline transceiver in 10 nm FinFET using MM-CDR-based ADC timing skew control and low-power DSP with approximate multiplier,” Proc. of 2020 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 122-124, 2020. [CrossRef]

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V. H.-C. Chen and L. Pileggi, “22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI,” Proc. of 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, pp. 380-381, 2014. [CrossRef]

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Y. Cao, M. Zhang, Y. Zhu, R. P. Martins, and C.-H. Chan, “A 12-GS/s 12-b 4× time-interleaved ADC using inputindependent timing skew calibration with global dither injection and linearized input buffer,” IEEE Journal of Solid- State Circuits, vol. 59, no. 12, pp. 4211-4224, December 2024. [CrossRef]

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B. Xu, Y. Zhou, and Y. Chiu, “A 23-mW 24-GS/s 6- bit voltage-time hybrid time-interleaved ADC in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1091-1100, April 2017. [CrossRef]

[11]

D.-R. Oh, M.-J. Seo, and S.-T. Ryu, “A 7-bit two-step flash ADC with sample-and-hold sharing technique,” IEEE Journal of Solid-State Circuits, vol. 57, no. 9, pp. 2791- 2801, September 2022. [CrossRef]

[12]

D.-R. Oh, J.-I. Kim, M.-J. Seo, J.-G. Kim, and S.-T. Ryu, “A 6-bit 10-GS/s 63-mW 4× TI time-domain interpolating flash ADC in 65-nm CMOS,” Proc. of ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 2015. [CrossRef]

[13]

Y. Zhu, T. Liu, S. K. Kaile, S. Kiran, I.-M. Yi, and R. Liu, “A 38-GS/s 7-bit pipelined-SAR ADC with speed - Enhanced bootstrapped switch and output level shifting technique in 22-nm FinFET,” IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2300-2313, August 2023. [CrossRef]

[14]

S. Cai, E. Z. Tabasy, A. Shafik, S. Kiran, S. Hoyos, and S. Palermo, “A 25 GS/s 6b TI two-stage multi-bit search ADC with soft-decision selection algorithm in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2168-2179, August 2017. [CrossRef]

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Y. Duan and E. Alon, “A 6b 46GS/s ADC with > 23GHz BW and sparkle-code error correction,” Proc. of 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan, pp. C162-C163, 2015. [CrossRef]

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K. Sun, G. Wang, Q. Zhang, S. Elahmadi, and P. Gui, “A 56-GS/s 8-bit time-interleaved ADC with ENOB and BW enhancement techniques in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 821-833, March 2019. [CrossRef]

[17]

A. S. Yonar, P. A. Francese, M. Brändli, M. Kossel, T. Morf, and J. E. Proesel, “An 8-bit 56GS/s 64× timeinterleaved ADC with bootstrapped sampler and class-AB buffer in 4nm CMOS,” Proc. of 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, pp. 168-169, 2022. [CrossRef]

[18]

L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, and M. Braendli, “22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS,” Proc. of 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, pp. 378-379, 2014. [CrossRef]

[19]

L. Kull, D. Luu, C. Menolfi, M. Braendli, P. A. Francese, and T. Morf, “A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and > 30dB SNDR at nyquist in 14nm CMOS FinFET,” Proc. of 2018 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 358-360, 2018. [CrossRef]

[20]

D.-S. Jo, B.-R.-S. Sung, M.-J. Seo, W.-C. Kim, and S.-T. Ryu, “A 40-nm CMOS 7-b 32-GS/s SAR ADC with background channel mismatch calibration,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 610-614, April 2020. [CrossRef]

[21]

D.-R. Oh, A 6-bit 20 GS/s time-interleaved two-step flash ADC in 40 nm CMOS,” Electronics, vol. 11, no. 19, 3052, 2022. [CrossRef]