1. First Stage Decimation
The first stage decimation consists of the timing aligner and the DFF array. Fig. 6 shows a block diagram of the timing aligner. The timing aligner operates by receiving two inputs: the reset signal, RST, which controls the on-off state of the test mode, and one of the sampling clocks from the sub-ADCs, designated as the reference clock for the decimation circuit, $Φ_1$. It outputs an enable signal, EN, which is synchronized with $Φ_1$. When RST transitions to a low state, EN is generated after two falling edges of $Φ_1$. This EN signal is critical in the proposed two-rank decimation technique, as it determines the digital output sequence.
Fig. 7 shows the block diagram of the 1/5 clock divider circuit using the EN signal shown in Fig. 6. The clock divider is implemented using 5-bit ring counters. It uses five DFFs and utilizes $Φ_1$, $Φ_3$ for input clock signals and EN for set and reset signals. It consists of two slices that receive $Φ_1$ and $Φ_3$ as inputs, and generates clocks $Φ_{D1}$[3], $Φ_{D1}$[4], $Φ_{D3}$[1], and $Φ_{D3}$[2] used for division. Because it is assumed to be 4 channels, it is divided into 1/5, and if the number of channels is N, it is designed to be the 1/(N+1) clock divider. As shown in Fig. 6, because EN is synchronized with $Φ_1$, whenever EN becomes high, the falling edge of $Φ_3$ occurs first, followed by the falling edge of $Φ_1$. It is synchronized to each of these falling edge to produce $Φ_{D1}$[3], $Φ_{D1}$[4], $Φ_{D3}$[1], and $Φ_{D3}$[2]. These clocks are used in DFF array to decimate the output of ADC.
Note that, slice 1 shown in Fig. 7 is first operated by the EN synchronized with $Φ_1$ to generate $Φ_{D3}$[1] and $Φ_{D3}$[2]. This allows the sub-ADC outputs to be multiplexed sequentially. If EN becomes “high” after falling edge of $Φ_3$, as shown in Fig. 5, there is a problem in which DM is output as 5, 6, 11, and 20 instead of 1, 6, 11, and 16. Therefore, sufficient clearance was designed between EN and $Φ_3$ to ensure that EN always operates first. If the interval between EN and $Φ_1$ is assumed to be $T_d$, the interval between the falling edge of $Φ_1$ and the falling edge of $Φ_3$ is assumed to be $T_s$, and the setup time of DFF is assumed to be $T_{set}$, it is designed to satisfy the condition of $T_d$ + $T_{set}$ < Ts/2. Therefore, the design synchronizes EN with two falling edges of $Φ_1$ to ensure a more stable generation of the EN signal.
Block and timing diagram of the 1/5 clock divider.
Block and timing diagrams for the MUX CLKGEN.
Block diagram of the MUX.
2. MUX CLK GEN and MUX
Fig. 8 shows a block and timing diagram of the MUX CLKGEN. The MUX CLKGEN can generate $Φ_M$ which is used as the master clock for the MUX. As shown in Fig. 4, the MUX sequentially merges $D_{D1~D4}$, the output of the DFF array obtained by the first stage decimation filter, into $D_M$ by synchronizing with $Φ_M$. As shown in Fig. 8, $Φ_M$ can be generated using the $Φ_{D1}$ and $Φ_{D3}$ signals, which are obtained by dividing $Φ_1$ and $Φ_3$ by 1/5 as shown in Fig. 7. Since $Φ_M$ generates regions with different periods every four cycles, the MUX outputs a wide digital code every four cycles. This characteristic does not cause issues when the digital code, $D_M$, and the capture clock, $Φ_M$, are synchronized.
Fig. 9 shows a block diagram of a 4 to 1 MUX. In the actual verification, the conversion speed of the TI ADC is 20GS/s, while the proposed two-rank decimation technique allows the MUX to operate at around 1 GHz. The design comprises four slices that receive the outputs of the 4 channels and the selection signal as the input. The 4-channel output data are connected to the OR gate, and the final output $D_M$[6:1] is generated.
Block and timing diagrams of the second stage decimation circuit (DECI).
Block diagram of the proposed two-rank decimation technique illustrated with a 16-channel TI ADC.
3. Second Stage Decimation
The second stage decimation circuit can use the same method used in conventional TI ADC architectures thanks to the MUX operation speed is greatly slowed down by the first stage decimation. Fig. 10 shows a block and timing diagrams of the second stage decimation circuit (DECI) used in this design. As shown in Fig. 10, in this design, $D_M$ is transferred to $D_{OUT}$ by the $Φ_{CAP}$ divided by 1/27. Keep in mind that the decimation factor of 1/27 can be selectively applied according to the desired frequency of $Φ_{CAP}$. However, the decimation factor must be chosen that allows the digital output codes of all sub-ADCs to be obtained. In conclusion, the proposed two-rank decimation technique, comprising digital blocks 1 through 3 as described in Section III, reduces the operating speed of the MUX to a level comparable to that of the sub-ADC. This improvement enhances channel scalability and facilitates real-time measurements with a reduced area compared to memory.