I. INTRODUCTION

Analog-to-digital converters (ADCs) are primarily used in IoT sensors and communication systems ^[1,2,3]. In particular, tens of GS/s ADCs are essential for PAM4-based wireline and 5G wireless communication systems ^[4,5,6,7]. However, because the digital logic at the back end of an ADC typically only operates at a few GHz, a single-channel ADC is limited in its ability to achieve over Giga-Hertz sampling rates. Therefore, time-interleaved (TI) ADC architectures, which use multiple ADCs in parallel and merge their outputs to achieve higher sampling rates, are often used ^[8,9,10].

Fig. 1 shows a conventional architecture using decimation, assuming $N$ channels and a sampling frequency of $f_s$ ^{[11,12,13,14]}. Each sub-ADC operates by sampling at a rate of $f_s/N$, while the MUX that merges their outputs operates at a rate of $f_s$. The output, $D_{\rm OUT}$, can also be processed using a decimation circuit with a frequency of $f_{\rm deci}$, which is in the Mega-Hertz range, allowing for real-time measurements. Note that the TI ADC conducts digital operations by parallelizing the outputs of each channel and merging them into one using a multiplexer (MUX). Therefore, the MUX must output data at the same rate as the sampling frequency of the TI ADC. As the sampling rate of the TI ADC increases, the speed burden on the MUX also increases, making implementation challenging.

Fig. 1. Conventional decimation logic-based digital output technique in TI ADCs ^{[11,12,13,14]}.

Fig. 2. Conventional memory-based digital output technique in TI ADCs ^{[15,16,17,18,19,20]}.

To address this, high-speed TI ADCs use measurement memory to store the digital output signals from each channel and then output the stored signals externally at a slower clock rate, as shown in Fig. 2 ^{[15,16,17,18,19,20]}. The digital output of each sub-ADC is stored in the subsequent memory block at a rate of $f_s/N$. The stored signals are then transmitted to the external environment of the chip through a parallel-to-serial memory interface operating at a slower speed. The utilization of memory requires a certain capacity (e.g., 6144 bits for a 1024 samples fast Fourier transform (FFT) of 6-bit resolution) to ensure the accuracy of ADC performance evaluation. As a result, it demands substantial area, and real-time performance evaluation is more challenging compared to decimation circuit-based measurement technique.

In this paper, we propose a two-rank decimation technique where the digital outputs of each channel are first decimated to a speed corresponding to the number of channels in the TI ADC before being merged using the MUX. The output of the MUX is then decimated once more to a speed that can be accommodated by the external measurement equipment. This approach aims to reduce the speed burden on the MUX to a level comparable to the conversion speed of the sub-ADC, minimize the area requirements, and enable real-time measurements. We validated this technique by applying it to a 6-bit, 20 GS/s time-interleaved two-step Flash ADC designed using a 40 nm CMOS process ^[21]. This paper discusses the same IC presented in ^[21] to validate the proposed technique but primarily focuses on explaining its architecture and operating principle. The proposed technique can also be applied to TI ADCs using different types of sub-ADCs, reducing the design burden on the MUX of the TI ADC.

This paper is organized as follows. Section II describes the proposed decimation architecture and timing diagram. The detailed implementation of the MUX and decimation circuit is described in Section III. Section IV describes the measurement results such as die photo, FFT, and PCB. Finally, Section V describes the conclusion.

II. ARCHITECTURE

Fig. 3 shows the proposed two-rank decimation technique. Before multiplexing the digital outputs of multi-channel ADCs, the digital output of the sub-ADC with a frequency of $f_s/N$ passes through $1/(N+1)$ decimation filters. The digital outputs from each decimation filter are merged in a MUX operating at a frequency of $f_s/(N+1)$. As shown in Fig. 3, the conventional decimation technique illustrated in Fig. 1 requires the MUX to operate at a speed of $f_s$, whereas the proposed technique allows it to operate at a speed of $f_s/(N+1)$. Moreover, even if the operating speed of the TI ADC increases by using a greater number of interleaving channels, the proposed technique ensures that the MUX always operates at a frequency reduced by a factor of $N+1$. This allows it to maintain the operating speed level of a single-channel ADC, thereby significantly reducing the speed burden compared to conventional architecture.

Fig. 3. Proposed two-rank decimation technique.

Fig. 4. Conceptual block diagram of the proposed two-rank decimation technique illustrated with a 4-channel TI ADC example.

Fig. 5. Timing diagram for Fig. 4.

Fig. 4 shows the conceptual block diagram of the proposed two-rank decimation technique. The actual verified architecture is 16-channel interleaved ADC. However, to simplify the explanation, we assumed only 4-channel architecture. The overall architecture consists of 4-channel ADCs, a DFF array, a 1/5 clock divider for the first stage decimation, a timing aligner that determines the start time of the 1/5 divider, and a second stage decimation circuit consisting of DECI, MUX, and MUX CLKGEN. The sequence of operations for the overall circuit is as follows: the ADCs that sample the input signal $V_{\rm IN}$ operate at a frequency of $f_s/4$ to match the respective ADC clocks ($\Phi_{1\sim 4}$) to generate digital outputs $D_{\rm A1\sim A4}$. The generated outputs $D_{\rm A1\sim A4}$ pass through the DFF array, merge in the MUX, and pass through the second stage decimation circuit to output a measurably slow 6-bit signal $D_{\rm OUT}$. The timing aligner, 1/5 clock divider and MUX CLK GEN circuits that generate the clocks used by the DFF array and MUX in this process are considered as the core circuits of the proposed architecture.

Fig. 5 shows the timing diagram of the circuit from Fig. 4. The clock operation is described assuming four channels for explanation, however, it may vary depending on the number of channels and their divided levels. When the RST is high, the circuit remains in the reset state, and when the RST goes low, EN goes high on the second falling edge of $\Phi_{1}$. This synchronizes EN to the falling edge of $\Phi_{1}$, ensuring that the first falling edge of $\Phi_{3}$ is always ahead of the first falling edge of $\Phi_{1}$ after EN goes high. In this way, the clocks come in the order of $\Phi_{\rm D3} [2]$, $\Phi_{\rm D3}[1]$, $\Phi_{\rm D1}[3]$, and $\Phi_{\rm D1}[4]$ are output, starting with the data on channel 2. EN must be synchronized with RST and $\Phi_{1}$, while the 1/5 clock divider is synchronized by EN to divide the clock. Section III describes the detailed circuit implementation and operation of each block.

III. CIRCUIT IMPLEMENTATION

1. First Stage Decimation

The first stage decimation consists of the timing aligner and the DFF array. Fig. 6 shows a block diagram of the timing aligner. The timing aligner operates by receiving two inputs: the reset signal, RST, which controls the on-off state of the test mode, and one of the sampling clocks from the sub-ADCs, designated as the reference clock for the decimation circuit, $\Phi_{1}$. It outputs an enable signal, EN, which is synchronized with $\Phi_{1}$. When RST transitions to a low state, EN is generated after two falling edges of $\Phi_{1}$. This EN signal is critical in the proposed two-rank decimation technique, as it determines the digital output sequence.

Fig. 6. Block and timing diagram of the timing aligner.

Fig. 7. Block and timing diagram of the 1/5 clock divider.

Fig. 7 shows the block diagram of the 1/5 clock divider circuit using the EN signal shown in Fig. 6. The clock divider is implemented using 5-bit ring counters. It uses five DFFs and utilizes $\Phi_{1}$, $\Phi_{3}$ for input clock signals and EN for set and reset signals. It consists of two slices that receive $\Phi_{1}$ and $\Phi_{3}$ as inputs, and generates clocks $\Phi_{\rm D1}[3]$, $\Phi_{\rm D1}[4]$, $\Phi_{\rm D3}[1]$, and $\Phi_{\rm D3}[2]$ used for division. Because it is assumed to be 4 channels, it is divided into 1/5, and if the number of channels is N, it is designed to be the $1/(N+1)$ clock divider. As shown in Fig. 6, because EN is synchronized with $\Phi_{1}$, whenever EN becomes high, the falling edge of $\Phi_{3}$ occurs first, followed by the falling edge of $\Phi_{1}$. It is synchronized to each of these falling edge to produce $\Phi_{\rm D1}[3]$, $\Phi_{\rm D1}[4]$, $\Phi_{\rm D3}[1]$, and $\Phi_{\rm D3}[2]$. These clocks are used in DFF array to decimate the output of ADC.

Note that, slice 1 shown in Fig. 7 is first operated by the EN synchronized with $\Phi_{1}$ to generate $\Phi_{\rm D3}[1]$ and $\Phi_{\rm D3}[2]$. This allows the sub-ADC outputs to be multiplexed sequentially. If EN becomes ?high? after falling edge of $\Phi_{3}$, as shown in Fig. 5, there is a problem in which $D_{\rm M}$ is output as 5, 6, 11, and 20 instead of 1, 6, 11, and 16. Therefore, sufficient clearance was designed between EN and $\Phi_{3}$ to ensure that EN always operates first. If the interval between EN and $\Phi_{1}$ is assumed to be $T_{\rm d}$, the interval between the falling edge of $\Phi_{1}$ and the falling edge of $\Phi_{3}$ is assumed to be $T_{\rm s}$, and the setup time of DFF is assumed to be $T_{\rm set}$, it is designed to satisfy the condition of $T_{\rm d} + T_{\rm set} < T_{\rm s}/2$. Therefore, the design synchronizes EN with two falling edges of $\Phi_{1}$ to ensure a more stable generation of the EN signal.

2. MUX CLK GEN and MUX

Fig. 8 shows a block and timing diagram of the MUX CLKGEN. The MUX CLKGEN can generate $\Phi_{\rm M}$ which is used as the master clock for the MUX. As shown in Fig. 4, the MUX sequentially merges $D_{\rm D1\sim D4}$, the output of the DFF array obtained by the first stage decimation filter, into $D_{\rm M}$ by synchronizing with $\Phi_{\rm M}$. As shown in Fig. 8, $\Phi_{\rm M}$ can be generated using the $\Phi_{\rm D1}$ and $\Phi_{\rm D3}$ signals, which are obtained by dividing $\Phi_{1}$ and $\Phi_{3}$ by 1/5 as shown in Fig. 7. Since $\Phi_{\rm M}$ generates regions with different periods every four cycles, the MUX outputs a wide digital code every four cycles. This characteristic does not cause issues when the digital code, $D_{\rm M}$, and the capture clock, $\Phi_{\rm M}$, are synchronized.

Fig. 8. Block and timing diagrams for the MUX CLKGEN.

Fig. 9. Block diagram of the MUX.

Fig. 9 shows a block diagram of a 4 to 1 MUX. In the actual verification, the conversion speed of the TI ADC is 20 GS/s, while the proposed two-rank decimation technique allows the MUX to operate at around 1 GHz. The design comprises four slices that receive the outputs of the 4 channels and the selection signal as the input. The 4-channel output data are connected to the OR gate, and the final output $D_{\rm M}[6:1]$ is generated.

3. Second Stage Decimation

The second stage decimation circuit can use the same method used in conventional TI ADC architectures thanks to the MUX operation speed is greatly slowed down by the first stage decimation. Fig. 10 shows a block and timing diagrams of the second stage decimation circuit (DECI) used in this design. As shown in Fig. 10, in this design, $D_{\rm M}$ is transferred to $D_{\rm OUT}$ by the $\Phi_{\rm CAP}$ divided by 1/27. Keep in mind that the decimation factor of 1/27 can be selectively applied according to the desired frequency of $\Phi_{\rm CAP}$. However, the decimation factor must be chosen that allows the digital output codes of all sub-ADCs to be obtained. In conclusion, the proposed two-rank decimation technique, comprising digital blocks 1 through 3 as described in Section III, reduces the operating speed of the MUX to a level comparable to that of the sub-ADC. This improvement enhances channel scalability and facilitates real-time measurements with a reduced area compared to memory.

Fig. 10. Block and timing diagrams of the second stage decimation circuit (DECI).

IV. MEASUREMENT RESULTS

Fig. 11 shows a prototype 6-bit 16-channel TI two-step flash ADC designed with 20 GS/s using the 40nm CMOS process ^[21]. Comparing Fig. 11 and Fig. 4, the actual verification circuit uses 16 sub-ADCs and 1/17 clock dividers, and four clocks for the clock divider. Therefore, the conditions mentioned in Fig. 6 are applied as $T_{\rm d} +T_{\rm set}<T_{\rm s}/4$ rather than $T_{\rm d} +T_{\rm set}<T_{\rm s}/2$. $T_{\rm d}$ was designed to be about 37 ps, $T_{\rm s}/4$ was designed to be about 200 ps, and the set time $T_{\rm set}$ of DFF was designed to be about 163 ps. In conclusion, it is designed to have sufficient timing margin. The following content describes the measurement results of the 16-channel ADC.

Fig. 11. Block diagram of the proposed two-rank decimation technique illustrated with a 16-channel TI ADC.

Fig. 12. Die photograph.

Fig. 12 shows a die photograph. The conventional DFF-based memory and the proposed two-rank decimation circuit are implemented on-chip for performance evaluation of the 16-channel TI ADC. The memory occupies an active area of 0.09 mm${}^{2}$ and can store 1024-points FFT. On the other hand, the proposed two-rank decimation logic occupies an active area of 0.007 mm${}^{2}$, which is much smaller than the memory-based data acquisition.

Fig. 13 shows a measurement setup. The input and clock signals are differentially applied. The digital output of the ADC is measured in two ways to compare the results measured by the decimator and memory. In the case of decimation, real-time data is decimated and transmitted to the PC through the NI-PCI-6552 board, and in the case of memory, data is stored according to the frequency of the memory, and this data is transmitted to the PC through the NI-PCI-6552 board like decimation to measure the final performance.

Fig. 14 shows the FFT results measured using the two-rank decimation technique. The signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and signal-to-noise and distortion ratio (SNDR) are measured to be 31.02, 40.23, and 30.12 dB, respectively, at a sampling rate of 20 GS/s and an input of 9.042 GHz. The SNR shown in Fig. 14 is limited by sampling clock jitter noise. Considering the designed noises such as comparator noise, quantization noise, and KT/C noise, it is expected that the sampling clock jitter noise is approximately 360 fs,rms.

Fig. 15 shows the power breakdown. The power consumption of the proposed circuit is 0.78 mW in total. The DECI, MUX, MUX CLKGEN, 1/17 clock divider, DFF array and timing aligner consume 0.29 mW, 0.1 mW, 0.05 mW, 0.17 mW, 0.11 mW, and 0.06 mW, respectively.

Table 1 summarizes the performance of the TI ADC applied to the proposed two-rank decimation technique and compares its performances with a 6-8 bits TI ADC architecture using memory with measured sampling frequencies greater than 20 GS/s. In structures using memory, the memory area has a size of at least 0.156 mm${}^{2}$ up to 0.994 mm${}^{2}$. The proposed two-rank decimation technique can also be applied to TI ADC architectures with 64 or more channels ^{[17,18,19,20]}. When applying the proposed technique to a 64-channel implementation, the condition $T_{\rm d} + T_{\rm set}<T_{\rm s}/8$ is satisfied, ensuring the stable generation of the EN signal. Additionally, each circuit can be designed according to the number of channels, enabling sufficient scalability.

By comparison, using two-rank decimation has a much smaller 0.013 mm${}^{2}$ than the memory area. When the prototype 6-bit TI two-step flash ADC was designed using two methods of memory and decimation, the memory area was designed to be 0.09 mm${}^{2}$ and the decimation area was 0.007 mm${}^{2}$, and the decimation area was designed to be about 8% of the memory area.

Fig. 13. Measurement setup for the 6-bit 20GS/s 16-channel TI ADC.

Fig. 14. Measured FFT spectra using the proposed two-rank decimation technique at 20 GS/s sampling rate with a 9.042 GHz input.

Fig. 15. Power breakdown of the proposed two-rank decimator.

Table 1. Performance comparison.

V. CONCLUSIONS

In this paper, we propose a two-rank decimation technique that can perform decimation in two stages to alleviate the speed burden of the MUX required for performance evaluation of TI ADCs and to facilitate real-time measurement environments. The proposed technique is verified using a 6-bit 20Gs/s 16-channel TI ADC architecture using a 40-nm CMOS process. The proposed decimation technique enables real-time data analysis without the need to accumulate and store data, unlike memory-based data acquisition methods, which require data accumulation and storage. Therefore, the proposed two-rank decimation technique could be implemented in an area of 0.007 mm${}^{2}$, compared to 0.09 mm${}^{2}$ of the memory-based data acquisition method implemented together in the same chip.