1. Influence of Channel Hole Diameter on 3D NAND Flash Memory

To investigate the impact of the channel hole geometry, device characteristics were analyzed by varying $d_{hole}$ with fixed parameters of $t_{ONO} = 17\text{ nm}$, $t_{ch} = 7\text{ nm}$, and $L_g = 24\text{ nm}$. Fig. 2(a) shows the $I_{BL}$-$V_{WL}$ curves for both pristine and programmed states under the same bias condition. As shown in Fig. 2(b), reducing $d_{hole}$ leads to a monotonic increase in $V_{th}$ and a steeper $SS$, which is consistent with the well-known electrostatic advantage of macaroni-type gate-all-around (GAA) structures. Thus, reducing the $d_{hole}$ strengthens the gate controllability over the channel potential, thereby suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and $V_{th}$ roll-off ^{[21, 22]}.

Fig. 2. (a) IBL-VWL characteristics of the 3D NAND flash memory cells with various channel hole diameter (dhole). 20 V program bias and 8 µs program time are applied to pristine cells. (b) The trend of threshold voltage (Vth) and subthreshold swing (SS) with various dhole. Vth is extracted using constant current method from a BL current (IBL) of 1 nA. (c) Radial electric field distribution during program operation. (d) IBL according to the overdrive voltage (Vov).

The program characteristics are also strongly affected by the $d_{hole}$. The programmed $V_{th}$ increases as $d_{hole}$ shrinks, primarily driven by the progressive widening of the program window ($\Delta V_{th}$) between the pristine and programmed states, as shown in Fig. 2(b). This phenomenon is attributed to the electric field curvature effect inherent to cylindrical structures ^{[23, 24]}. Fig. 2(c) shows the radial electric-field distribution across the ONO stack during program operation. As the curvature radius decreases, the electric field across the tunneling oxide increases significantly, whereas the field in the blocking oxide is slightly relaxed. This geometry-induced field enhancement exponentially boosts the Fowler-Nordheim (FN) tunneling from channel to CTL while mitigating the back tunneling from CTL to gate, thereby maximizing programming efficiency.

On the other hand, $I_{BL}$ exhibits an opposite trend. Fig. 2(d) shows $I_{BL}$ as a function of the $d_{hole}$ for various overdrive voltages ($V_{ov} = V_{WL} - V_{th\text{, programmed}}$). At a fixed $V_{ov} = 1.5\text{ V}$, $I_{BL}$ increases almost linearly with $d_{hole}$. This behavior arises because the thin macaroni body operates under quasi-volume inversion, where the inversion layer extends across the entire silicon shell, rendering the effective conduction width proportional to the channel circumference ^{[21, 25]}. This reflects a fundamental trade-off: smaller channels provide superior program efficiency at the expense of reduced drive current. However, under the low-$V_{ov}$ conditions relevant to multi-level operation, the current difference between large and small diameters becomes less pronounced because the improved $SS$ of the smaller-diameter cells compensates for the reduced perimeter. Thus, properly optimized small-diameter channels can simultaneously secure a wide program window and sufficient read current within a limited memory window, which is favorable for high-density multi-level 3D NAND flash memory.

2. Influence of Fabrication-Induced Variations on 3D NAND Flash Memory

Structural non-idealities originating from HAR etching are represented by an elliptic channel hole, whose distortion is quantified by the ellipticity ^[26]. Fig. 3(a) depicts that the programmed $V_{th}$ decreases as the ellipticity increases, whereas the $I_{BL}$ monotonically increases as shown in Fig. 3(b). When the circular channel is distorted into an ellipse, the local radius of curvature varies along the perimeter: the regions near the major axis have a smaller curvature radius, whereas those near the minor axis exhibit a larger curvature radius. Under such conditions, the gate electric field is more weakly coupled to the channel in the minor-axis sectors, which induces weak program efficiency. Thus, the programmed $V_{th}$ is determined by the weakly-controlled minor-axis region, and increasing ellipticity further enlarges the local curvature radius, leading to a reduction of the global $V_{th}$ ^{[17, 27]}. In addition, this $V_{th}$ degradation is more sensitive to the smaller $d_{hole}$. Since the electric field in the tunneling oxide is inversely proportional to the curvature radius, the sensitivity of the field to geometric distortion is significantly higher for smaller dimensions. Thus, even for the same ellipticity, the increase in the curvature radius at the minor axis induces a much steeper reduction of the electric field in the tunneling oxide for a smaller $d_{hole}$, resulting in a more severe deterioration of the programmed $V_{th}$.

Fig. 3. (a) Vth and (b) IBL of the programmed 3D NAND flash memory cells according to the elliptic hole profile distortion. The ellipticity (a/b) is adjusted by altering only the length of the major axis while maintaining the length of the minor axis.

Fig. 4. (a) Vth and (b) IBL of the programmed 3D NAND flash memory cells with various thickness of ONO stacks (tONO). The relative thickness ratio of the oxide/nitride/oxide layers is kept constant, and only the total ONO stack thickness is varied.

In contrast, the trend of $I_{BL}$ is predominantly governed by the channel cross-section rather than by the curvature-induced variation of the local $V_{th}$. Under read conditions with a sufficiently large $V_{ov}$ the entire channel perimeter is driven into inversion. Thus, increasing ellipticity which enlarges the cross-sectional area at a fixed length of minor axis, leads to a monotonic increase in $I_{BL}$.

Fig. 4 illustrates the impact of $t_{ONO}$ variation induced during the deposition process. A thicker ONO stack reduces the tunneling electric field and increases the tunneling distance during programming, which lowers the injected charge density in the CTL and reduces the programmed $V_{th}$. The sensitivity of $V_{th}$ to $t_{ONO}$ becomes weaker as $d_{hole}$ decreases, since the strong radial confinement in small-diameter GAA channels concentrates the electric field in the tunneling oxide and partially compensates for variations of the physical oxide thickness. In contrast, the dependence of $I_{BL}$ on $t_{ONO}$ is relatively weak (Fig. 4(b)); a slight reduction of current with increasing $t_{ONO}$ is attributed to the reduction of the cross-sectional area of the silicon channel.

3. Temperature Dependency of the Read Operation

The effect of operating temperature on the programmed state is illustrated in Fig. 5. As the read temperature increases from 300 K to 373 K, the programmed $V_{th}$ gradually shifts to lower values for all channel diameters (Fig. 5(a)). This trend originates from the intrinsic temperature dependence of $V_{th}$ in MOSFETs: with increasing temperature, the intrinsic carrier concentration rises, and the Fermi potential decreases, leading to a reduction in $V_{th}$ even in the absence of additional charge loss in the CTL ^[11]. In poly-Si channels, the $V_{th}$ degradation becomes more severe because the potential barrier at grain boundaries is also lowered as temperature increases, which further facilitates carrier transport ^[13].

Fig. 5. (a) Vth and (b) IBL of the programmed 3D NAND flash memory cells according to the read temperature. The program operation is performed at 300 K.

The $I_{BL}$ exhibits a more pronounced temperature dependence. Fig. 5(b) shows that $I_{BL}$ decreases monotonically with increasing read temperature when a fixed $V_{ov}$ is maintained. It is owing to the degradation of $SS$ which is proportional to the temperature. In the subthreshold and near-threshold region relevant to multi-level sensing, the current further decreases because both the thermal voltage and the $SS$ increase with temperature, reducing the exponential factor in the $I_{BL}$ expression. Thus, high-temperature operation simultaneously lowers the apparent $V_{th}$ and suppresses the read current, effectively narrowing the sensing margin. These results highlight the necessity of reference voltage calibration and compensation schemes in deeply scaled 3D NAND flash, particularly when small-diameter channels are adopted for high-density multi-level operation.