Performance Analysis on Silicon Bridge with Chessboard Patterned Interconnect
Seung Kyu Kim1
Ji-Hoon Kang1
Kee-Won Kwon1,*
-
College of Information and Communication Engineering, Sungkyunkwan University, Suwon-si,
Gyeonggi-do, Korea
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index terms
Advanced packaging, heterogeneous integration, signal integrity (SI), crosstalk mitigation, universal chiplet interconnect express (UCIe)
I. INTRODUCTION
Advanced packaging technologies have become essential for meeting the growing performance
demands of high-performance computing (HPC) and AI-driven big data applications. Heterogeneous
integration has emerged as a key enabler in achieving higher interconnect density,
greater bandwidth, and improved power efficiency [1,
2]. Among various approaches, 2.5D integration using silicon-based interconnect technologies,
such as Si interposers and Si bridges, has gained significant attention [3-
7]. While Si interposers provide high-density routing with through-silicon vias (TSVs),
they are often associated with higher cost and fabrication complexity due to their
large-area processing, and they may also introduce reliability concerns such as warpage
[8]. In contrast, the Si bridge offers a compact and cost-effective alternative by enabling
localized high-density die-to-die (D2D) connections without requiring full-area TSVs,
making it suitable for applications that demand both high performance and form-factor
efficiency [5-
7].
The Si bridge typically consists of a four-layer metal stack, with signal (S) and
ground (G) lines arranged in a vertical S-G-S-G format. This configuration ensures
that each signal line is effectively shielded by adjacent ground planes, commonly
referred to as the fully shielded (FS) structure, as shown in Fig. 1(b). Extensive research has focused on optimizing key design parameters including physical
dimensions, the signal-to-ground (GND) shield ratio, line spacing, and the placement
of shields within the signal layer [9]. However, despite these efforts, structural optimization for signal integrity remains
limited in its ability to scale interconnect density due to crosstalk noise.
To overcome the limitations of FS S1G1 configuration, which provides excellent signal
isolation but suffers from low routing density, the chessboard patterned interconnect
(CPI) configuration was proposed in our previous work, as shown in Fig. 1(c)
[10]. The CPI structure was developed by incorporating insights from metal interconnect
shielding and spacing metrics used for crosstalk noise suppression [11], along with studies on staggered signal-GND patterns implemented in two- or three-layer
substrates [12-
14]. The objective of CPI is to preserve shielding effectiveness while doubling the wire
routing density.
Fig. 1. (a) Conceptual cross-sectional view of a Si bridge for 2.5D packaging. 3D
Interconnect models with (b) a conventional fully shielded S1G1 (FS S1G1) and (c)
the proposed chessboard patterned interconnect (CPI) configuration.
In this paper, the CPI structure is redefined and evaluated based on the specifications
of the Universal Chiplet Interconnect express (UCIe) standard [15-
18]. UCIe is an open industry standard for D2D interconnects between heterogeneous chiplets,
providing practical and scalable design targets to address the demands of the compute
continuum. A comparative analysis with the conventional FS S1G1 configuration is performed
to quantify signal integrity and crosstalk performance at high data rate up to 32
Gbps. The modeling of Si bridge interconnects and the simulation methodology are described
in Section II. Section III presents simulation results comparing FS S1G1 and CPI structures
under the UCIe standard, focusing on improvements in signal quality and routing density
enabled by additional metal layers. Furthermore, structural optimization techniques
are introduced to ensure that crosstalk degradation in the CPI remains within acceptable
limits, even under high-speed conditions. Finally, leveraging the structural flexibility
of the CPI, we propose a selective signal-ground configuration method that enables
effective crosstalk mitigation while supporting application-specific routing requirements.
II. MODELING AND METHODOLOGY
To evaluate the effectiveness of the CPI configuration in Si bridges, a comparative
performance analysis was performed through simulation against the conventional FS
S1G1 structure. Fig. 2 illustrates the cross-sectional views of both configurations. The dimension parameters
and material properties used in the simulations are summarized in Table 1. A four-layer interconnect model was adopted, and both FS S1G1 and CPI structures
were modeled in accordance with UCIe design specifications. In advanced packaging,
the target channel length is typically less than 2 mm, measured from a bump on one
die to the corresponding bump on the opposite die [15]. To model the worst-case scenario, the channel length was set to 2 mm. This study
focuses exclusively on channel-level effects and does not include bump-level modeling,
in order to simplify the analysis and isolate the structural differences between the
two interconnect configurations. The thicknesses of the insulation and metal layers
were selected based on prior studies on Si bridge technology [9,
11]. Copper (Cu) was used for signal lines, and oxide was assumed for dielectric layers,
with corresponding dielectric constant and loss tangent applied.
Fig. 2. Cross-sectional views of Si bridge with (a) FS S1G1 configuration and (b)
CPI configuration along dashed A–A’ lines in Fig. 1.
Table 1. Dimension parameters and material properties.
|
Parameters
|
Values
|
|
Signal line width ($W_{\text{Signal}}$) / Thickness ($T_{\text{Signal}}$)
|
2 $\mu\text{m}$ / 2 $\mu\text{m}$
|
|
GND line width ($W_{\text{GND}}$) / Thickness ($T_{\text{GND}}$)
|
2 $\mu\text{m}$ / 2 $\mu\text{m}$
|
|
Space width ($W_{\text{Space}}$) / Thickness ($T_{\text{Space}}$)
|
2 $\mu\text{m}$ / 2 $\mu\text{m}$
|
|
Dielectric ($\text{SiO}_2$) relative permittivity
|
4.0
|
|
Dielectric ($\text{SiO}_2$) loss tangent
|
$1\times 10^{-4}$
|
|
Copper (Cu) conductivity
|
$5.8\times 10^7\text{ S/m}$
|
Full-3D electromagnetic (EM) simulations and time-domain simulations were employed
to analyze signal integrity, using Ansys HFSS and Circuit. The S-parameters generated
from the 3D EM solver simulations have been validated to show high correlation with
hardware measurements [19]. We employed full-3D EM simulation in this work, to achieve more accurate analysis
by implementing a meshed ground plane, unlike our previous studies and most conventional
signal integrity analyses of Si bridges, which typically assumed a solid ground plane
in the FS S1G1 configuration [9,
10,
12]. In practical packaging implementations, ground layers are often implemented using
meshed patterns to satisfy metal density constraints and mechanical reliability requirements
[22]. In addition, previous studies have demonstrated that interconnects referenced to
meshed ground planes can be accurately analyzed using full-wave electromagnetic simulations
and effective transmission-line modeling approaches [21]. Unlike 2D models, full 3D modeling enables accurate simulation of the spatial distribution
of electric and magnetic fields and provides a more precise representation of inductive
effects, critical for capturing physical phenomena such as crosstalk [13]. This enhanced accuracy facilitates a more reliable assessment of how structural
design changes, such as those between FS and CPI schemes, influence signal behavior.
For S-parameter matrix extraction, all channels were terminated with matched loads.
To assess not only the near-end crosstalk (NEXT) and far-end crosstalk (FEXT) of a
single adjacent aggressor, but also the cumulated effect of multiple surrounding aggressors,
power-sum NEXT (PSNEXT) and power-sum FEXT (PSFEXT) were calculated [20].
Furthermore, in the UCIe advanced channel standard, target values are defined for
loss and crosstalk based on the voltage transfer function (VTF), specifically VTF
loss (VTF L) and VTF crosstalk (VTF XT). Fig. 3 shows the testbench setup used for VTF-based extractions [15,
18]. To determine which component has the most significant impact on overall signal degradation,
both cumulative and individual analysis were conducted.
The same testbench conditions shown in Fig. 3 were also applied for the extraction of eye diagrams. To emulate a worst-case input
scenario, a pseudo-random bit sequence (PRBS) signal was used as the input stimulus
[7].
Fig. 3. Testbench for voltage transfer function loss (VTF L) and cumulative crosstalk
(VTF XT) extraction. The configuration is based on the UCIe advanced channel, with
0.25 pF and 25 $\Omega$ at the TX, and a 0.2 pF load at the unterminated RX [15, 18].
III. RESULTS AND DISCUSSION
1. FS S1G1 vs. CPI: Feasibility Under UCIe
A comparative analysis of the electrical transmission characteristics of the conventional
FS S1G1 and the proposed CPI configurations was carried out using S-parameters and
power-sum crosstalk extractions. Figs. 4(a) and 4(b) present the reflection loss ($S_{11}$) and insertion loss ($S_{21}$), respectively.
The CPI structure, which features reduced GND coverage, exhibits degraded $S_{11}$
and $S_{21}$ performance in both the M2 and M4 layers due to its lower shielding effectiveness,
compared to the FS structure with surrounding constant-potential GND lines. For NEXT
and FEXT, performance varies depending on the relative position of the aggressors,
as shown in Figs. 4(c) and 4(d). When evaluating orthogonally placed aggressors, the open-top M4 layer shows similar
behavior between CPI and FS S1G1. However, in the M2 layer, where the signal lines
are fully shielded in FS S1G1, the conventional structure provides superior isolation.
A key characteristic of the CPI configuration is the presence of additional diagonal
aggressor lines. Since these aggressors are positioned closer to the victim signal
lines than orthogonal ones, they induce strong crosstalk for both NEXT and FEXT. This
value is higher than that of the orthogonal aggressors in the M2 layer and is comparable
to that of the orthogonal aggressors in the M4 layer. To evaluate the cumulative interference
from all surrounding aggressors, PSNEXT and PSFEXT were extracted, as shown in Figs. 4(e) and 4(f). The CPI exhibits greater degradation in both M2 and M4 layers, with M2 showing a
more pronounced increase. This behavior is attributed to the higher number of diagonal
aggressors ($N_{DA}$) in M2 layer, which amplifies cumulative coupling impact.
Fig. 4. S-parameters of FS S1G1 and CPI configurations: (a) reflection loss, (b) insertion
loss, (c) near-end crosstalk (NEXT), (d) far-end crosstalk (FEXT), (e) power-sum NEXT
(PSNEXT), and (f) power-sum FEXT (PSFEXT).
The increased crosstalk leads to higher voltage coupling and timing jitter during
signal transmission, as demonstrated in the eye diagrams presented in Figs. 5(a) and 5(b). These diagrams correspond to a uniform data rate of 32 GT/s per layer for both FS
S1G1 and CPI. Despite the increased interference, the CPI structure still satisfies
the eye diagram requirements defined in the UCIe specification, as indicated by the
yellow reference boxes. A primary advantage of CPI is its ability to double the routing
density compared to FS S1G1, considering the number of signal lines per layer. To
achieve equivalent total routing density, FS S1G1 must operate at twice the data rate,
or CPI at half. The corresponding eye diagrams under these adjusted conditions are
shown in Figs. 5(c) and 5(d). In Fig. 5(c), FS S1G1 structure operating at 64 GT/s exhibits a closed eye, failing to meet the
required specifications. In contrast, Fig. 5(d) shows that CPI, operating at 16 GT/s, maintains a wider eye opening than Fig. 5(a), despite the same total routing density, thereby confirming its superior signal performance.
Fig. 5. Eye diagrams of (a) FS S1G1 and (b) CPI at 32 GT/s, (c) FS S1G1 at 64 GT/s,
and (d) CPI at 16 GT/s. The yellow rectangular boxes indicate the minimum eye-opening
requirements specified in UCIe.
To evaluate additional UCIe requirements beyond the eye diagram, VTF L and VTF XT
were extracted for both FS S1G1 and CPI, as shown in Figs. 6(a) and 6(b). Regions that fail to meet the specification thresholds are highlighted in color.
According to Table 2, the VTF criteria vary depending on data rate and are categorized into low-speed
signals (4 to 16 GT/s) and high-speed signals (24 and 32 GT/s). The reference frequency
for evaluation is the Nyquist frequency, defined as half the data rate, which must
satisfy both the VTF L and VTF XT requirements. Both configurations satisfy the VTF
L limits, maintaining values below 2 dB for low-speed signals and below 2.5 dB for
high-speed signals. According to the UCIe specification, the first condition of the
VTF XT requirement states that the VTF XT value must be lower than the result of subtracting
21.5 dB (for low-speed signals) or 19 dB (for high-speed signals) from 1.5 times the
VTF L at the Nyquist frequency. Therefore, the first condition becomes the stricter
requirement for low-speed signals, whereas the second condition dominates for high-speed
signals. As a result, as shown in Fig. 6(b), the effective requirement for VTF XT can be summarized as less than -24.5 dB for
low-speed and -24 dB for high-speed signals. While CPI satisfies the VTF XT criteria
for low-speed signals in both M2 and M4 layers, it fails to meet the high-speed specification.
This degradation is primarily attributed to increased diagonal coupling, consistent
with the PSNEXT results.
Fig. 6. (a) VTF L and (b) VTF XT of FS S1G1 and CPI Si bridge with the testbench shown
in Fig. 3.
Table 2. UCIe requirement on VTF.
|
Data rate [GT/s]
|
VTF loss [dB]
|
VTF crosstalk [dB]
|
|
4, 8, 12, 16
|
$L(f_N) > -3$
|
$XT(f_N) < 1.5L(f_N) - 21.5$
and $XT(f_N) < -23$
|
|
24, 32
|
$L(f_N) > -5$
|
$XT(f_N) < 1.5L(f_N) - 19.0$
and $XT(f_N) < -24$
|
Similar to the eye diagram analysis, the CPI satisfies the UCIe specifications when
operated under the same total routing density as FS S1G1. However, to fully exploit
its routing density advantage, additional reduction of crosstalk is required. Structural
approaches to achieve this are discussed in Sections III-3 and III-4.
2. FS SnG1 vs. CPI: Crosstalk with Routing Density Consideration
In the conventional FS configuration, a common method for increasing routing density
is to place multiple signal lines between two GND lines, forming an SnG1 structure,
as shown in Fig. 7(a)
[9]. The corresponding routing densities for various SnG1 configurations, in comparison
with the CPI, are summarized in Table 3. Even in the case of S4G1, which places four signal lines between adjacent GNDs,
the total routing density remains approximately 4% lower than that of the CPI configuration,
corresponding to a difference of 20 IO/mm.
Fig. 7. (a) Structures of SnG1 configuration. (b) VTF XT of the CPI and SnG1 configurations
as a function of the routing density on the M4 layer.
Table 3. Routing density based on configuration.
|
Configuration
|
FS SnG1
|
CPI
|
|
S1G1
|
S2G1
|
S3G1
|
S4G1
|
|
Number of signal layers
|
2
|
2
|
2
|
2
|
4
|
|
Routing density
|
[IO/mm/Layer]
|
125
|
167
|
200
|
240
|
125
|
|
[IO/mm]
|
250
|
333
|
400
|
480
|
500
|
Fig. 7(b) presents the VTF XT performance of FS SnG1 and CPI structures in the M4 layer, evaluated
at key frequency points. The SnG1 configurations from S2G1 to S4G1 consistently exhibit
inferior VTF XT characteristics compared to CPI. These results indicate that SnG1
structures fail to meet UCIe crosstalk specifications not only in the high-speed region
but also in most low-speed cases.
These results confirm that the spacing between a victim line and its nearest aggressor
is a dominant factor influencing crosstalk behavior. Even a single adjacent aggressor
can significantly impact the victim signal, as demonstrated by the S2G1 results. Moreover,
the similarity between S3G1 and S4G1 indicates a saturation effect, where additional
aggressors placed farther from both ends of the signal line contribute minimally to
further degradation. These findings support the conclusion that the CPI configuration
provides a more effective approach to increasing routing density while maintaining
acceptable crosstalk performance.
3. Crosstalk Mitigation via Ground Structuring
To ensure that the CPI configuration meets the VTF XT requirements at high-speed data
rates, structural modification techniques for suppressing crosstalk noise were investigated.
Initially, our focus is on crosstalk reduction through GND shielding enhancement.
This approach involves trade-offs with routing density.
Fig. 8(a) illustrates the structural modification when the width of the ground ($W_{\text{GND}}$)
is increased while maintaining alignment with the signal line center. Fig. 8(b) shows the corresponding trends in VTF XT and routing density for the M2 and M4 layers
as $W_{\text{GND}}$ increases at 32 GT/s. An increase of just 1 $\mu\text{m}$ in $W_{\text{GND}}$
is sufficient to satisfy the high-speed VTF XT requirements. The crossover point of
VTF XT between M2 and M4, observed at approximately 6 $\mu\text{m}$, represents a
transition where the benefit of topside GND shielding begins to outweigh the degradation
caused by a higher $N_{DA}$ in the M2 layer. When $W_{\text{GND}}$ reaches 10 $\mu\text{m}$,
the routing density of CPI becomes equivalent to that of the FS S1G1 configuration.
Fig. 8. (a) Cross-sectional views of CPI structure with WGND of 4 $\mu$m and 6 $\mu$m,
including a plane view along the dashed line. (b) Trends of VTF XT of M2 and M4 layers
at 32 GT/s, along with routing density, as a function of WGND.
Although ground structuring through $W_{\text{GND}}$ expansion effectively suppresses
crosstalk, it must adhere to design rules that limit the total metal coverage per
layer. Excessive metal area may lead to wafer warpage [8]. Therefore, large GND planes are typically implemented as meshed structures rather
than solid plate [21]. This implementation requires spacing between metal regions to be equivalent to the
metal width. As a result, either the space between GND shields ($W_{\text{SPACE}}$)
must increase with $W_{\text{GND}}$, or $W_{\text{SPACE}}$ must be allocated between
adjacent GND lines if $W_{\text{GND}}$ remains fixed. Consequently, although a $W_{\text{GND}}$
of 4 $\mu\text{m}$ may be sufficient to satisfy performance requirements, a $W_{\text{GND}}$
value of 6 $\mu\text{m}$ is more likely to be adopted in practice to maintain design
compliance while accommodating two GND lines and one spacing.
4. Selective Signal-Ground Configuration
The CPI structure offers high design flexibility due to its decoupled and layer-agnostic
configuration of signal and GND lines. In Si bridges, the speed requirements of interconnects
depend on several factors, including the number of high- and low-speed signal lines
required by the connected chiplets and the physical lengths of the interconnects.
Shorter signal lines are inherently more robust to crosstalk noise. However, their
lengths can vary based on bump placement, which typically has a pitch of 110 to 130
$\mu\text{m}$ [17], and on routing conditions, such as bottom-layer signals that must connect to distant
bumps on the opposite die.
Leveraging the structural flexibility of CPI, certain diagonal signal lines can be
selectively converted into GND lines. This approach significantly improves signal
quality and enables compliance with high-speed requirements. A conceptual diagram
of this selective configuration is shown in Fig. 9, where the $N_{DA}$ surrounding a victim line varies from 4 to 0. The resulting trends
of PSNEXT, PSFEXT, VTF L, and VTF XT are presented in Fig. 10.
Fig. 9. Cross-sectional views of CPI configuration as the number of diagonal aggressors
(NDA) adjacent to the victim signal line decreases from 4 to 0.
Fig. 10. (a) PSNEXT, and (b) PSFEXT of the CPI for NDA values from 4 to 0 and the
FS S1G1 configuration on the M2 layer. (c) VTF L and (d) VTF XT of the CPI for NDA
values from 4 to 0 on the M2 layer.
Figs. 10(a) and 10(b) show that both PSNEXT and PSFEXT gradually improve as the $N_{DA}$ decreases, with
a sharp drop when $N_{DA}$ reaches 0. This result indicates that even a single diagonal
aggressor can significantly degrade signal quality. When $N_{DA}$ is zero, the structure
approximates FS S1G1, with the victim signal nearly surrounded by GND shielding. However,
due to residual spacing, its performance remains slightly inferior. As shown in Figs. 10(c) and (d), VTF L improves as $N_{DA}$ decreases and VTF XT satisfies the high-speed UCIe criteria
when $N_{DA}$ is reduced to two or fewer, suggesting that partial GND replacement
is sufficient to meet requirements.
Although selectively replacing some signal lines with GND reduces routing density,
the overall density still exceeds that of FS S1G1. This enables the CPI structure
to support high-speed signal lines while retaining its density advantage. Fig. 11(a) presents the bit error rate (BER) analysis based on unit interval (UI) for varying
$N_{DA}$. According to the UCIe standard, the raw BER must remain below $10^{-15}$
[15]. The simulated values fall below $10^{-16}$ in all cases, confirming compliance.
Additionally, Fig. 11(b) shows that the eye opening, extracted at a BER level of $10^{-3}$, improves as $N_{DA}$
decreases.
Fig. 11. (a) Bit error rate (BER) bathtub curve and (b) eye opening at BER of $10^{-3}$
for the CPI with NDA values from 4 to 0.
The key advantage of the selective signal-GND configuration is that a uniform CPI-based
Si bridge can be fabricated regardless of specific electrical requirements. If signal-GND
routing adjustments are implemented near the chiplet I/O using programmable routing
layers or switchable interposers, the number of high-speed channels can be dynamically
reconfigured depending on the system demands or application scenarios. In this sense,
the CPI structure can be regarded as a routing template in which the physical interconnect
grid remains fixed while the functional assignment of signal and ground lines can
be flexibly adjusted depending on the chiplet I/O requirements.
IV. CONCLUSIONS
This paper presents a comprehensive evaluation of the CPI structure for Si bridge,
in comparison with conventional FS S1G1 and SnG1 configurations, demonstrating its
potential as a high-density interconnect solution under the UCIe standard. The CPI
configuration demonstrated superior routing density by leveraging staggered and multi-layer
signal arrangements, effectively doubling the interconnect capacity per unit length
compared to FS S1G1. Through simulation-based analysis, CPI was shown to significantly
improve routing density while maintaining compliance with key signal integrity requirements.
Although high-speed VTF XT remains a challenge due to the influence of diagonal aggressors,
the proposed mitigation strategies, $W_{\text{GND}}$ expansion and selective GND conversion,
provide viable pathways to enable compliance with minimum impact on routing density
and manufacturability. Overall, the proposed CPI structure provides a scalable and
efficient solution for high-density Si bridge designs and enables system-level optimization
for heterogeneous integration applications requiring scalable, high-speed chiplet
connectivity.
ACKNOWLEDGEMENTS
This work was supported by the Technology Innovation Program (RS-2023-00236091) grant
funded by the Ministry of Trade, Industry & Energy (MOTIE), and partly by the National
Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.
RS-2023-00239657).
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Seung Kyu Kim received the B.S. and M.S. degrees in electronic engineering from Sogang
University, Seoul, South Korea, in 2014 and 2016, respectively. He is currently pursuing
the Ph.D. degree in semiconductor display engineering from Sungkyunkwan University.
His current research interests include semiconductor devices and advanced packaging.
Ji-Hoon Kang received his B.S. degree from Korea Aerospace University and his M.S.
degree in semiconductor convergence engineering from Sungkyunkwan University in 2025.
His research interests include signal integrity analysis for advanced packaging.
Kee-Won Kwon received the B.S. degree in metallurgical engineering from Seoul National
University, Seoul, South Korea, in 1988, and the M.S. degree in electrical engineering
and the Ph.D. degree in materials science and engineering from Stanford University,
Stanford, CA, USA, in 2000 and 2001, respectively. From 1990 to 1995, he was with
Samsung Electronics, Yongin, South Korea, where he developed DRAM capacitors with
high-k dielectric thin films and successfully implemented them into commercial products.
In 2000, he led two digital-to-analog circuit design projects in Maxim Integrated
Products, Sunnyvale, CA, USA. He rejoined Samsung Electronics in 2001 and was involved
in high performance DRAM designs including Rambus DRAM and XDR DRAM. In 2007, he moved
to Sungkyunkwan University, Suwon, where he is doing research in areas including memory
IP design, applications of emerging non-volatile memories, and high-speed circuit
solutions for analog and mixed-signal systems.